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Maciej Bellos: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Maciej Bellos, Dimitrios Kagaris, Dimitris Nikolos
    Test Set Embedding Based on Phase Shifters. [Citation Graph (0, 0)][DBLP]
    EDCC, 2002, pp:90-101 [Conf]
  2. Maciej Bellos, Dimitris Nikolos
    Deterministic Test Vector Compression / Decompression Using an Embedded Processor. [Citation Graph (0, 0)][DBLP]
    EDCC, 2005, pp:318-331 [Conf]
  3. Maciej Bellos, Dimitris Nikolos, Haridimos T. Vergos
    Path Delay Fault Testing of a Class of Circuit-Switched Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    EDCC, 1999, pp:267-282 [Conf]
  4. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos, Xrysovalantis Kavousianos
    Low Power Testing by Test Vector Ordering with Vector Repetition. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:205-210 [Conf]
  5. Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos
    Scan Cell Ordering for Low Power BIST. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:281-284 [Conf]
  6. Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos
    Low Power Test Set Embedding Based on Phase Shifters. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:155-160 [Conf]
  7. Xrysovalantis Kavousianos, Dimitris Bakalis, Maciej Bellos, Dimitris Nikolos
    An Efficient Test Vector Ordering Method for Low Power Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:285-288 [Conf]
  8. Maciej Bellos, Xrysovalantis Kavousianos, Dimitris Nikolos, Dimitri Kagaris
    DV-TSE: Difference Vector Based Test Set Embedding. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:343-0 [Conf]
  9. Dimitris Bakalis, K. Adaos, D. Lymperopoulos, Maciej Bellos, Haridimos T. Vergos, George Alexiou, Dimitris Nikolos
    A core generator for arithmetic cores and testing structures with a network interface. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2006, v:52, n:1, pp:1-12 [Journal]
  10. Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou
    Deterministic BIST for RNS Adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:7, pp:896-906 [Journal]

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