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Publications of Author

1. Richard C. Yee, Sharad Saxena, Paul E. Utgoff, Andrew G. Barto
   Explaining Temporal Differences to Create Useful Concepts for Evaluating States. [Citation Graph (0, 0)][DBLP]
   AAAI, 1990, pp:882-888 [Conf]
   
2. Carlo Guardiani, Sharad Saxena, Patrick McNamara, Phillip Schumaker, Dale Coder
   An asymptotically constant, linearly bounded methodology for the statistical simulation of analog circuits including component mismatch effects. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:15-18 [Conf]
   
3. Carlo Guardiani, Patrick McNamara, Lidia Daldoss, Sharad Saxena, Stefano Zanella, Wei Xiang, Suli Liu
   Analog IP Testing: Diagnosis and Optimization. [Citation Graph (0, 0)][DBLP]
   DATE, 2002, pp:192-196 [Conf]
   
4. Sharad Saxena
   Evaluating alternative Instance Representations. [Citation Graph (0, 0)][DBLP]
   ML, 1989, pp:465-468 [Conf]
   
5. Sharad Saxena
   On the Effect of Instance Representation on Generalization. [Citation Graph (0, 0)][DBLP]
   ML, 1991, pp:198-202 [Conf]
   
6. Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng
   Application Specific Worst Case Corners Using Response Surfaces and Statistical Models. [Citation Graph (0, 0)][DBLP]
   ISQED, 2004, pp:351-356 [Conf]
   
7. Marko P. Chew, Sharad Saxena, Thomas F. Cobourn, Purnendu K. Mozumder, Andrzej J. Strojwas
   A New Methodology for Concurrent Technology Development and Cell Library Optimization. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1999, pp:18-25 [Conf]
   
8. Manidip Sengupta, Sharad Saxena, Lidia Daldoss, Glen Kramer, Sean Minehane, Jianjun Cheng
   Application-specific worst case corners using response surfaces and statistical models. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1372-1380 [Journal]
   
9. Maxim Ershov, Sharad Saxena, Sean Minehane, P. Clifton, Mark Redford, R. Lindley, H. Karbasi, S. Graves, S. Winters
   Degradation dynamics, recovery, and characterization of negative bias temperature instability. [Citation Graph (0, 0)][DBLP]
   Microelectronics Reliability, 2005, v:45, n:1, pp:99-105 [Journal]