The SCEAS System
Navigation Menu

Search the dblp DataBase


Eiichi Takahashi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Neil Marston, Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi, Toshio Adachi, Kaoru Takasuka
    An Evolutionary Approach to GHz Digital Systems. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2000, pp:125-132 [Conf]
  2. Eiichi Takahashi, Masahiro Murakawa, Yuji Kasai, Tetsuya Higuchi
    Power Dissipation Reductions with Genetic Algorithms. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2003, pp:111-116 [Conf]
  3. Yuji Kasai, Eiichi Takahashi, Masaya Iwata, Yosuke Iijima, Hidenori Sakanashi, Masahiro Murakawa, Tetsuya Higuchi
    Adaptive Waveform Control in a Data Transceiver for Multi-speed IEEE1394 and USB Communication. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:198-204 [Conf]
  4. Prashant R. Chandra, Allan Fisher, Corey Kosak, T. Ng, Peter Steenkiste, Eiichi Takahashi, Hui Zhang
    Darwin: Customizable Resource Management for Value-Added Network Services. [Citation Graph (0, 0)][DBLP]
    ICNP, 1998, pp:177-188 [Conf]
  5. Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi
    The Execution Model and the Architecture for Real-Time Parallel Systems. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1994, pp:177-182 [Conf]
  6. Shigeru Kusakabe, Eiichi Takahashi, Rin-ichiro Taniguchi, Makoto Amamiya
    Dataflow-Based Lenient Implementation of a Functional Language, Valid, on Conventional Multi-processors. [Citation Graph (0, 0)][DBLP]
    IFIP PACT, 1994, pp:279-288 [Conf]
  7. Shigeru Kusakabe, Eiichi Takahashi, Rin-ichiro Taniguchi, Makoto Amamiya
    A Dataflow-Based Massively Parallel Programming Language and Its Implementation. [Citation Graph (0, 0)][DBLP]
    PARLE, 1994, pp:761-764 [Conf]
  8. Heejo Lee, Kenji Toda, Jong Kim, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi
    Performance comparison of real-time architectures using simulation. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1995, pp:150-0 [Conf]
  9. Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi
    CODA-R: a reconfigurable testbed for real-time parallel computation. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1997, pp:252-259 [Conf]
  10. Kenji Toda, Kenji Nishida, Eiichi Takahashi, Yoshinori Yamaguchi
    A Priority Forwarding Router Chip for Real-Time Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1994, pp:63-73 [Conf]
  11. Masahiro Murakawa, Eiichi Takahashi, Tatsuya Susa, Tetsuya Higuchi
    Post-fabrication clock timing adjustment for digital LSIs with genetic algorithms ensuring timing margins. [Citation Graph (0, 0)][DBLP]
    SMC (4), 2004, pp:3670-3674 [Conf]
  12. Tetsuya Higuchi, Masaya Iwata, Didier Keymeulen, Hidenori Sakanashi, Masahiro Murakawa, Isamu Kajitani, Eiichi Takahashi, Kenji Toda, Mehrdad Salami, Nobuki Kajihara, Nobuyuki Otsu
    Real-world applications of analog and digital evolvable hardware . [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Evolutionary Computation, 1999, v:3, n:3, pp:220-235 [Journal]

  13. Adaptive Optical Proximity Correction Using an Optimization Method. [Citation Graph (, )][DBLP]

  14. Post-Fabrication Clock-Timing Adjustment for Digital LSIs Ensuring Operational Timing Margins. [Citation Graph (, )][DBLP]

  15. Proposal for LDPC Code Design System Using Multi-Objective Optimization and FPGA-Based Emulation. [Citation Graph (, )][DBLP]

  16. World-Wide Accessible LDPC Encoder/Decoder Generator Using Web-Based GUI and API. [Citation Graph (, )][DBLP]

  17. Proposal of transmission line modeling using multi-objective optimization techniques. [Citation Graph (, )][DBLP]

Search in 0.002secs, Finished in 0.003secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002