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Juan Manuel Moreno: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany, E. Cantó, Rafal Kielbik, Julio Faura, Josep Maria Insenser
    Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 1999, pp:182-187 [Conf]
  2. Juan Manuel Moreno, Yann Thoma, Eduardo Sanchez, Oriol Torres, Gianluca Tempesti
    Hardware Realization of a Bio-inspired POEtic Tissue. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2004, pp:237-244 [Conf]
  3. Leos Kafka, Rafal Kielbik, Rudolf Matousek, Juan Manuel Moreno
    VPart: an automatic partitioning tool for dynamic reconfiguration (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:263- [Conf]
  4. E. Cantó, Juan Manuel Moreno, Joan Cabestany, Julio Faura, Josep Maria Insenser
    A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic. [Citation Graph (0, 0)][DBLP]
    FPL, 1999, pp:134-143 [Conf]
  5. E. Cantó, Juan Manuel Moreno, Joan Cabestany, I. Lacadena, Josep Maria Insenser
    Implementation of Virtual Circuits by Means of the FIPSOC Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:87-95 [Conf]
  6. Julio Faura, Juan Manuel Moreno, Miguel Angel Aguirre Echánove, Phuoc van Duong, Josep Maria Insenser
    Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor. [Citation Graph (0, 0)][DBLP]
    FPL, 1997, pp:1-10 [Conf]
  7. Rafal Kielbik, Juan Manuel Moreno, Andrzej Napieralski, Grzegorz Jablonski, Tomasz Szymanski
    High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:271-280 [Conf]
  8. Juan Manuel Moreno, Jordi Madrenas, Eduard Alarcón, Joan Cabestany
    Analog Sequential Architecture for Neuro-Fuzzy Models VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    ICANN, 1997, pp:1199-1204 [Conf]
  9. Juan Manuel Moreno, Javier Iglesias, Jan Eriksson, Alessandro E. P. Villa
    Physical Mapping of Spiking Neural Networks Models on a Bio-inspired Scalable Architecture. [Citation Graph (0, 0)][DBLP]
    ICANN (1), 2006, pp:936-943 [Conf]
  10. Jan Eriksson, Oriol Torres, Andrew Mitchell, Gayle Tucker, Ken Lindsay, David M. Halliday, Jay Rosenberg, Juan Manuel Moreno, Alessandro E. P. Villa
    Spiking Neural Networks for Reconfigurable POEtic Tissue. [Citation Graph (0, 0)][DBLP]
    ICES, 2003, pp:165-173 [Conf]
  11. Juan Manuel Moreno, Jan Eriksson, Javier Iglesias, Alessandro E. P. Villa
    Implementation of Biologically Plausible Spiking Neural Networks Models on the POEtic Tissue. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:188-197 [Conf]
  12. Juan Manuel Moreno, Jordi Madrenas, Julio Faura, E. Cantó, Joan Cabestany, Josep Maria Insenser
    Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices. [Citation Graph (0, 0)][DBLP]
    ICES, 1998, pp:345-355 [Conf]
  13. Juan Manuel Moreno, Yann Thoma, Eduardo Sanchez
    POEtic: A Prototyping Platform for Bio-inspired Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 2005, pp:177-187 [Conf]
  14. Andrew M. Tyrrell, Eduardo Sanchez, Dario Floreano, Gianluca Tempesti, Daniel Mange, Juan Manuel Moreno, Jay Rosenberg, Alessandro E. P. Villa
    POEtic Tissue: An Integrated Architecture for Bio-inspired Hardware. [Citation Graph (0, 0)][DBLP]
    ICES, 2003, pp:129-140 [Conf]
  15. F. Castillo, Joan Cabestany, Juan Manuel Moreno
    An Integrated Circuit for Artificial Neural Networks. [Citation Graph (0, 0)][DBLP]
    IWANN, 1991, pp:328-332 [Conf]
  16. F. Castillo, Joan Cabestany, Juan Manuel Moreno
    Region of Influence (ROI) Networks. Model and Implementation. [Citation Graph (0, 0)][DBLP]
    IWANN, 1993, pp:96-101 [Conf]
  17. F. Castillo, Jose A. García, Juan Manuel Moreno, Joan Cabestany
    A Coprocessor Card for Fast Neural Network Emulation. [Citation Graph (0, 0)][DBLP]
    IWANN, 1995, pp:752-760 [Conf]
  18. A. Chinea, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany
    Improving the Performance of Piecewise Linear Separation Incremental Algorithms for Practical Hardware Implementations. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:607-616 [Conf]
  19. Jordi Madrenas, Gregorio Ruiz, Juan Manuel Moreno, Joan Cabestany
    Synthesis and Optimization of a Bit-Serial Pipeline Kernel Processor. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:801-810 [Conf]
  20. N. Maria, Anne Guérin-Dugué, Juan Manuel Moreno, François Blayo
    Comparing Implementations of Radial Basis Function Neural Networks on Three Parallel Machines. [Citation Graph (0, 0)][DBLP]
    IWANN, 1995, pp:771-780 [Conf]
  21. José Matas, Luis García de Vicuña, Mariano López, Juan Manuel Moreno
    A Fuzzy Controller for Switching Regulators with Programmable Control Surfaces. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:851-860 [Conf]
  22. Juan Manuel Moreno, F. Castillo, Joan Cabestany
    Optimiized Learning for Improving the Evolution of Piecewise Linear Separation Incremental Algorithms. [Citation Graph (0, 0)][DBLP]
    IWANN, 1993, pp:272-277 [Conf]
  23. Juan Manuel Moreno, Joan Cabestany, E. Cantó, Julio Faura, Josep Maria Insenser
    The Role of Dynamic Reconfiguration for Implementing Artificial Neural Networks Models in Programmable Hardware. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 1999, pp:85-94 [Conf]
  24. Juan Manuel Moreno, Jordi Madrenas, S. San Anselmo, F. Castillo, Joan Cabestany
    Digital Hardware Implementation of ROI Incremental Algorithms. [Citation Graph (0, 0)][DBLP]
    IWANN, 1995, pp:761-770 [Conf]
  25. Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany, J. R. Laúna
    Using Classical and Evolutive Neural Models in Industrial Applications: A Case Study for an Automatic Coin Classifier. [Citation Graph (0, 0)][DBLP]
    IWANN, 1997, pp:922-931 [Conf]
  26. Oriol Torres, Jan Eriksson, Juan Manuel Moreno, Alessandro E. P. Villa
    Hardware Optimization of a Novel Spiking Neuron Model for the POEtic Tissue. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 2003, pp:113-120 [Conf]
  27. Raquel Paricio, Juan Manuel Moreno
    POEtic-cubes: acquisition of new qualia through apperception using a bio-inspired electronic tissue. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2005, pp:783-789 [Conf]
  28. Yann Thoma, Eduardo Sanchez, Daniel Roggen, Carl Hetherington, Juan Manuel Moreno
    Prototyping with a Bio-Inspired Reconfigurable Chip. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:239-246 [Conf]
  29. E. Cantó, Juan Manuel Moreno, Joan Cabestany, I. Lacadena, Josep Maria Insenser
    A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:210-218 [Journal]

  30. The Perplexus bio-inspired reconfigurable circuit. [Citation Graph (, )][DBLP]


  31. A Novel Hardware Architecture for Self-adaptive Systems. [Citation Graph (, )][DBLP]


  32. PERPLEXUS: Pervasive Computing Framework for Modeling Complex Virtually-Unbounded Systems. [Citation Graph (, )][DBLP]


  33. JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator. [Citation Graph (, )][DBLP]


  34. SpiNDeK: An Integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks. [Citation Graph (, )][DBLP]


  35. A reconfigurable architecture for emulating large-scale bio-inspired systems. [Citation Graph (, )][DBLP]


  36. BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications. [Citation Graph (, )][DBLP]


  37. A Consensus Model for Group Decision Making with Incomplete Unbalanced Fuzzy Linguistic Preference Relations. [Citation Graph (, )][DBLP]


  38. Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture. [Citation Graph (, )][DBLP]


  39. Improving the Performance of PieceWise Linear Separation Incremental Algorithms for Practical Hardware Implementations [Citation Graph (, )][DBLP]


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