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Russell P. Kraft: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Channakeshav, Kuan Zhou, Russell P. Kraft, John F. McDonald
    Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic. [Citation Graph (0, 0)][DBLP]
    Evolvable Hardware, 2002, pp:60-62 [Conf]
  2. Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, Young Uk Yim, Robert W. Heikaus, Russell P. Kraft, John F. McDonald
    A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:181-187 [Conf]
  3. Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    The gigahertz FPGA: design consideration and applications. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:248- [Conf]
  4. Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:145-153 [Conf]
  5. Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda
    A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:248- [Conf]
  6. Bryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald
    Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:59-69 [Conf]
  7. Chao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonald
    A 11 GHz FPGA with Test Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:101-105 [Conf]
  8. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonald
    Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:11-20 [Conf]
  9. Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:414-423 [Conf]
  10. Jong-Ru Guo, Chao You, Paul F. Curran, Michael Chu, Kuan Zhou, Jiedong Diao, A. George, Russell P. Kraft, John F. McDonald
    The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:141-144 [Conf]
  11. John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald, Russell P. Kraft
    3D direct vertical interconnect microprocessors test vehicle. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:141-146 [Conf]
  12. Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald
    A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:37-40 [Conf]
  13. Jong-Ru Guo, Chao You, Michael Chu, Okan Erdogan, Russell P. Kraft, John F. McDonald
    A High Speed Reconfigurable Gate Array for Gigahertz Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:124-129 [Conf]
  14. Young Uk Yim, John F. McDonald, Russell P. Kraft
    12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator with Hybrid Control Schemes. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:278-279 [Conf]
  15. Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald
    Predicting the Performance of a 3D Processor-Memory Chip Stack. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:540-547 [Journal]
  16. Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:525-540 [Journal]
  17. Kuan Zhou, Jong-Ru Guo, Chao You, John Mayega, Russell P. Kraft, T. Zhang, John F. McDonald, Bryan S. Goda
    Multi-ghz Sige Bicmos Fpgas with New Architecture and Novel Power Management Techniques. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:2, pp:179-194 [Journal]
  18. Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald
    Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:212-219 [Journal]
  19. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Peter F. Curran, Kuan Zhou, Bryan S. Goda, John F. McDonald
    A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:121-131 [Journal]
  20. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Bryan S. Goda, John F. McDonald
    A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1051-1054 [Journal]
  21. Pete M. Campbell, Hans J. Greub, Atul Garg, A. Steidl, Steven R. Carlough, Matthew W. Ernest, Robert F. Philhower, Cliff A. Maier, Russell P. Kraft, John F. McDonald
    A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:52-55 [Journal]

  22. Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking. [Citation Graph (, )][DBLP]


  23. Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers. [Citation Graph (, )][DBLP]


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