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Hafizur Rahaman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hafizur Rahaman, Debesh K. Das
    A Simple Delay Testable Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    AACC, 2004, pp:263-270 [Conf]
  2. Hafizur Rahaman, Debesh K. Das
    Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:172-177 [Conf]
  3. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    A New Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:160-165 [Conf]
  4. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:224-229 [Conf]
  5. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:287-0 [Conf]
  6. Sukanta Das, Hafizur Rahaman, Biplab K. Sikdar
    Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:284-287 [Conf]
  7. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:284-289 [Conf]
  8. Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta
    Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design. [Citation Graph (0, 0)][DBLP]
    IICAI, 2005, pp:232-251 [Conf]
  9. Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta
    Minimum-Congestion Placement for Y-interconnects: Some studies and observations. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:73-80 [Conf]
  10. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    A New Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:160-165 [Conf]
  11. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:487-492 [Conf]
  12. H. Rahaman, Jimson Mathew, Dhiraj K. Pradhan
    Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:479-484 [Conf]
  13. H. Rahaman, Jimson Mathew, B. K. Sikdar, Dhiraj K. Pradhan
    Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:422-430 [Conf]
  14. Susmit Bagchi, Hafizur Rahaman, Purnendu Das
    MDVM System Concept, Paging Latency and Round-2 Randomized Leader Election Algorithm in SG. [Citation Graph (0, 0)][DBLP]
    JACIII, 2006, v:10, n:5, pp:752-760 [Journal]
  15. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. [Citation Graph (0, 0)][DBLP]
    J. Comput. Sci. Technol., 2002, v:17, n:6, pp:731-737 [Journal]
  16. Jimson Mathew, H. Rahaman, Dhiraj K. Pradhan
    Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:207-208 [Conf]
  17. Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta
    A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  18. Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
    Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2006, v:22, n:2, pp:125-142 [Journal]

  19. A novel droplet routing algorithm for digital microfluidic biochips. [Citation Graph (, )][DBLP]


  20. On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element. [Citation Graph (, )][DBLP]


  21. C-testable S-box implementation for secure advanced encryption standard. [Citation Graph (, )][DBLP]


  22. On the design of different concurrent EDC schemes for S-Box and GF(p). [Citation Graph (, )][DBLP]


  23. Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. [Citation Graph (, )][DBLP]


  24. Revisiting fidelity: a case of elmore-based Y-routing trees. [Citation Graph (, )][DBLP]


  25. On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. [Citation Graph (, )][DBLP]


  26. Design of Reversible Finite Field Arithmetic Circuits with Error Detection. [Citation Graph (, )][DBLP]


  27. A Galois Field Based Logic Synthesis Approach with Testability. [Citation Graph (, )][DBLP]


  28. Single Error Correcting Finite Field Multipliers Over GF(2m). [Citation Graph (, )][DBLP]


  29. A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. [Citation Graph (, )][DBLP]


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