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Debesh K. Das: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Hafizur Rahaman, Debesh K. Das
A Simple Delay Testable Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP]
AACC, 2004, pp:263-270 [Conf] - Debesh K. Das, Susanta Chakraborty, Bhargab B. Bhattacharya
Interchangeable Boolean Functions and Their Effects on Redundancy in Logic Circuits. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 1998, pp:469-474 [Conf] - Hafizur Rahaman, Debesh K. Das
Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2005, pp:172-177 [Conf] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
A New Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2002, pp:160-165 [Conf] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2004, pp:224-229 [Conf] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 1999, pp:287-0 [Conf] - Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2002, pp:671-676 [Conf] - Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri
Cellular automata as a built in self test structure. [Citation Graph (0, 0)][DBLP]
ASP-DAC, 2001, pp:319-324 [Conf] - Debesh K. Das, Bhargab B. Bhattacharya
Testable design of non-scan sequential circuits using extra logic. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 1995, pp:176-0 [Conf] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 2003, pp:284-289 [Conf] - Biplab K. Sikdar, Samir Roy, Debesh K. Das
Enhancing BIST Quality of Sequential Machines through Degree-of-Freedom Analysis. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 2001, pp:285-0 [Conf] - Biplab K. Sikdar, Arijit Sarkar, Samir Roy, Debesh K. Das
Synthesis of Testable Finite State Machine Through Decomposition. [Citation Graph (0, 0)][DBLP]
Asian Test Symposium, 2005, pp:398-403 [Conf] - Susanta Chakraborty, Sandip Das, Debesh K. Das, Bhargab B. Bhattacharya
Synthesis of Symmetric Functions for Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1999, pp:512-517 [Conf] - Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1998, pp:205-0 [Conf] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
A New Synthesis of Symmetric Functions. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2002, pp:160-165 [Conf] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2004, pp:487-492 [Conf] - Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das
Degree-of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2002, pp:671-676 [Conf] - Biplab K. Sikdar, Sukanta Das, Samir Roy, Niloy Ganguly, Debesh K. Das
Cellular Automata Based Test Structures with Logic Folding. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2005, pp:71-74 [Conf] - Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly
Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. [Citation Graph (0, 0)][DBLP]
VLSI Design, 2001, pp:403-0 [Conf] - Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya
Isomorph-redundancy in sequential circuits. [Citation Graph (0, 0)][DBLP]
VTS, 1996, pp:463-469 [Conf] - Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian
Design & Test Education in Asia. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 2004, v:21, n:4, pp:331-338 [Journal] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. [Citation Graph (0, 0)][DBLP]
J. Comput. Sci. Technol., 2002, v:17, n:6, pp:731-737 [Journal] - Debesh K. Das, Uttam K. Bhattacharya, Bhargab B. Bhattacharya
Isomorph-Redundancy in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 2000, v:49, n:9, pp:992-997 [Journal] - Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
J. Electronic Testing, 2006, v:22, n:2, pp:125-142 [Journal] - Biplab K. Sikdar, Samir Roy, Debesh K. Das
A Degree-of-Freedom Based Synthesis Scheme for Sequential Machines with Enhanced BIST Quality and Reduced Area. [Citation Graph (0, 0)][DBLP]
J. Electronic Testing, 2005, v:21, n:1, pp:83-93 [Journal]
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