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Harish Patil: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Harish Patil, Charles N. Fischer
    Efficient Run-time Monitoring Using Shadow Processing. [Citation Graph (0, 0)][DBLP]
    AADEBUG, 1995, pp:119-132 [Conf]
  2. Chi-Keung Luk, Robert Muth, Harish Patil, Robert S. Cohn, P. Geoffrey Lowney
    Ispike: A Post-link Optimizer for the Intel®Itanium®Architecture. [Citation Graph (0, 0)][DBLP]
    CGO, 2004, pp:15-26 [Conf]
  3. Harish Patil, Joel S. Emer
    Combining Static and Dynamic Branch Prediction to Reduce Destructive Aliasing. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:251-0 [Conf]
  4. Chi-Keung Luk, Robert Muth, Harish Patil, Richard Weiss, P. Geoffrey Lowney, Robert S. Cohn
    Profile-guided post-link stride prefetching. [Citation Graph (0, 0)][DBLP]
    ICS, 2002, pp:167-178 [Conf]
  5. Harish Patil, Robert S. Cohn, Mark Charney, Rajiv Kapoor, Andrew Sun, Anand Karunanidhi
    Pinpointing Representative Portions of Large Intel® Itanium® Programs with Dynamic Instrumentation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2004, pp:81-92 [Conf]
  6. Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish Patil, Artur Klauser, P. Geoffrey Lowney, Steven Wallace, Vijay Janapa Reddi, Kim M. Hazelwood
    Pin: building customized program analysis tools with dynamic instrumentation. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:190-200 [Conf]
  7. Le-Chun Wu, Rajiv Mirani, Harish Patil, Bruce Olsen, Wen-mei W. Hwu
    A New Framework for Debugging Globally Optimized Code. [Citation Graph (0, 0)][DBLP]
    PLDI, 1999, pp:181-191 [Conf]
  8. Satish Narayanasamy, Cristiano Pereira, Harish Patil, Robert Cohn, Brad Calder
    Automatic logging of operating system effects to guide application-level architecture simulation. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS/Performance, 2006, pp:216-227 [Conf]
  9. Joel S. Emer, Pritpal Ahuja, Eric Borch, Artur Klauser, Chi-Keung Luk, Srilatha Manne, Shubhendu S. Mukherjee, Harish Patil, Steven Wallace, Nathan L. Binkert, Roger Espasa, Toni Juan
    Asim: A Performance Model Framework. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:2, pp:68-76 [Journal]
  10. Harish Patil, Charles N. Fischer
    Low-Cost, Concurrent Checking of Pointer and Array Accesses in C Programs. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1997, v:27, n:1, pp:87-110 [Journal]
  11. Dhananjay M. Dhamdhere, Harish Patil
    An Elimination Algorithm for Bidirectional Data Flow Problems Using Edge Placement. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Program. Lang. Syst., 1993, v:15, n:2, pp:312-336 [Journal]

  12. PinPlay: a framework for deterministic replay and reproducible analysis of parallel programs. [Citation Graph (, )][DBLP]


  13. Cross Binary Simulation Points. [Citation Graph (, )][DBLP]


  14. Reproducible simulation of multi-threaded workloads for architecture design exploration. [Citation Graph (, )][DBLP]


  15. Analyzing Parallel Programs with Pin. [Citation Graph (, )][DBLP]


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