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Vijay Janapa Reddi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Alex Shye, Matthew Iyer, Vijay Janapa Reddi, Daniel A. Connors
    Code coverage testing using hardware performance monitoring support. [Citation Graph (0, 0)][DBLP]
    AADEBUG, 2005, pp:159-163 [Conf]
  2. Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Matthew Iyer, Dan Fay, David Hodgdon, Joshua L. Kihm, Alex Settle, Dirk Grunwald, Daniel A. Connors
    Dynamic run-time architecture techniques for enabling continuous optimization. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2005, pp:211-220 [Conf]
  3. Vijay Janapa Reddi, Dan Connors, Robert Cohn, Michael D. Smith
    Persistent Code Caching: Exploiting Code Reuse Across Executions and Applications. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:74-88 [Conf]
  4. Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Dirk Grunwald, Ramesh Peri
    Shadow Profiling: Hiding Instrumentation Costs with Parallelism. [Citation Graph (0, 0)][DBLP]
    CGO, 2007, pp:198-208 [Conf]
  5. Silvia M. Figueira, Vijay Janapa Reddi
    Topology-Based Hypercube Structures for Global Communication in Heterogeneous Networks. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2005, pp:994-1004 [Conf]
  6. Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
    A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:271-282 [Conf]
  7. Chi-Keung Luk, Robert S. Cohn, Robert Muth, Harish Patil, Artur Klauser, P. Geoffrey Lowney, Steven Wallace, Vijay Janapa Reddi, Kim M. Hazelwood
    Pin: building customized program analysis tools with dynamic instrumentation. [Citation Graph (0, 0)][DBLP]
    PLDI, 2005, pp:190-200 [Conf]
  8. Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vijay Janapa Reddi, Dan Connors, Youfeng Wu, Jin Lee, David Brooks
    Dynamic-Compiler-Driven Control for Microprocessor Energy and Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:1, pp:119-129 [Journal]
  9. Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Joseph Blomstedt, Daniel A. Connors
    Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    DSN, 2007, pp:297-306 [Conf]

  10. Software-assisted hardware reliability: abstracting circuit-level challenges to the software stack. [Citation Graph (, )][DBLP]


  11. An event-guided approach to reducing voltage noise in processors. [Citation Graph (, )][DBLP]


  12. Voltage emergency prediction: Using signatures to reduce operating margins. [Citation Graph (, )][DBLP]


  13. Web search using mobile cores: quantifying and mitigating the price of efficiency. [Citation Graph (, )][DBLP]


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