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Peter Bellows: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peter Bellows
    Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:247-258 [Conf]
  2. Peter Bellows, Jaroslav Flidr, Tom Lehman, Brian Schott, Keith D. Underwood
    GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:121-130 [Conf]
  3. Peter Bellows, Brad L. Hutchings
    JHDL - An HDL for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:175-0 [Conf]
  4. Brad L. Hutchings, Peter Bellows, Joseph Hawkins, K. Scott Hemmert, Brent E. Nelson, Mike Rytting
    A CAD Suite for High-Performance FPGA Design. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:12-24 [Conf]
  5. Peter Bellows, Jaroslav Flidr, Ladan Gharai, Colin Perkins, Pawel Chodowiec, Kris Gaj
    IPsec-Protected Transport of HDTV over IP. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:869-879 [Conf]
  6. Pawel Chodowiec, Kris Gaj, Peter Bellows, Brian Schott
    Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. [Citation Graph (0, 0)][DBLP]
    ISC, 2001, pp:220-234 [Conf]
  7. Tim Grembowski, Roar Lien, Kris Gaj, Nghi Nguyen, Peter Bellows, Jaroslav Flidr, Tom Lehman, Brian Schott
    Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512. [Citation Graph (0, 0)][DBLP]
    ISC, 2002, pp:75-89 [Conf]
  8. Peter Bellows
    High-Visibility Debug-By-Design for FPGA Platforms. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2005, v:32, n:2, pp:105-118 [Journal]

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