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Publications of Author

1. Razali Jidin, David L. Andrews, Douglas Niehaus
   Implementing Multi Threaded System Support for Hybrid FPGA/CPU Computational Components. [Citation Graph (0, 0)][DBLP]
   ERSA, 2004, pp:116-122 [Conf]
   
2. David L. Andrews, Ron Sass, Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp
   The Case for High Level Programming Models for Reconfigurable Computers. [Citation Graph (0, 0)][DBLP]
   ERSA, 2006, pp:21-32 [Conf]
   
3. Erik Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David L. Andrews
   Enabling a Uniform Programming Model Across the Software/Hardware Boundary. [Citation Graph (0, 0)][DBLP]
   FCCM, 2006, pp:89-98 [Conf]
   
4. David L. Andrews, Joe Evans, Venumadhav Mangipudi, Aditya Mandapaka
   SCIMPS: An Integrated Approach to Distributed Processing in Sensor Webs. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:111- [Conf]
   
5. David L. Andrews, Douglas Niehaus
   Architectural Frameworks for MPP Systems on a Chip. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:265- [Conf]
   
6. David L. Andrews, Lonnie R. Welch, David M. Chelberg, Scott A. Brandt
   A Framework for Using Benefit Functions In Complex Real Time Systems. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2002, pp:- [Conf]
   
7. Razali Jidin, David L. Andrews, Wesley Peck, Dan Chirpich, Kevin Stout, John M. Gauch
   Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2005, pp:- [Conf]
   
8. Jason Agron, Wesley Peck, Erik Anderson, David L. Andrews, Ed Komp, Ron Sass, Fabrice Baijot, Jim Stevens
   Run-Time Services for Hybrid CPU/FPGA Systems on Chip. [Citation Graph (0, 0)][DBLP]
   RTSS, 2006, pp:3-12 [Conf]
   
9. Douglas Niehaus, David L. Andrews
   Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation. [Citation Graph (0, 0)][DBLP]
   WORDS Fall, 2003, pp:317-324 [Conf]
   
10. David L. Andrews, Douglas Niehaus, Peter J. Ashenden
    Programming Models for Hybrid CPU/FPGA Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:1, pp:118-120 [Journal]
    
11. William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg
    Seeking Solutions in Configurable Computing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1997, v:30, n:12, pp:38-43 [Journal]
    
12. Daniel Pease, Arif Ghafoor, Ishfaq Ahmad, David L. Andrews, Kamal Foudil-Bey, Thomas E. Karpinski, Mohammad A. Mikki, Mohamed Zerrouki
    PAWS: A Performance Evaluation Tool for Parallel Computing Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:18-29 [Journal]
    
13. David L. Andrews, Paul Austin, Peter Costello, David LeVan
    Interprocess communications in the AN/BSY-2 distributed computer system: a case study. [Citation Graph (0, 0)][DBLP]
    Journal of Systems and Software, 2002, v:61, n:3, pp:233-242 [Journal]
    
14. David L. Andrews, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge L. Ortiz, Ed Komp, Peter J. Ashenden
    Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2004, v:24, n:4, pp:42-53 [Journal]
    
15. Wesley Peck, Erik Anderson, Jason Agron, Jim Stevens, Fabrice Baijot, David L. Andrews
    Hthreads: A Computational Model for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
    
16. 
    Building heterogeneous reconfigurable systems with a hardware microkernel. [Citation Graph (, )][DBLP]
    
    
17. 
    Modeling Abstractions for Next Generation Reconfigurable Computing. [Citation Graph (, )][DBLP]
    
    
18. 
    Memory Hierarchy for MCSoPC Multithreaded Systems. [Citation Graph (, )][DBLP]
    
    
19. 
    Supporting High Level Language Semantics Within Hardware Resident Threads. [Citation Graph (, )][DBLP]
    
    
20. 
    Building heterogeneous reconfigurable systems using threads. [Citation Graph (, )][DBLP]
    
    
21. 
    Hardware Microkernels for Heterogeneous Manycore Systems. [Citation Graph (, )][DBLP]
    
    
22. 
    Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs. [Citation Graph (, )][DBLP]