The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Michael Chu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chris Olston, Allison Woodruff, Alexander Aiken, Michael Chu, Vuk Ercegovac, Mark Lin, Mybrid Spalding, Michael Stonebraker
    DataSplash. [Citation Graph (1, 2)][DBLP]
    SIGMOD Conference, 1998, pp:550-552 [Conf]
  2. Jong-Ru Guo, Chao You, Michael Chu, Kuan Zhou, Young Uk Yim, Robert W. Heikaus, Russell P. Kraft, John F. McDonald
    A Novel Multi-Speed, Power Saving Architecture for SiGe HBT FPGA. [Citation Graph (0, 0)][DBLP]
    Engineering of Reconfigurable Systems and Algorithms, 2003, pp:181-187 [Conf]
  3. Michael Chu, Nicholas Weaver, Kolja Sulimma, André DeHon, John Wawrzynek
    Object Oriented Circuit-Generators in Java. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:158-166 [Conf]
  4. Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    The gigahertz FPGA: design consideration and applications. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:248- [Conf]
  5. Yury Markovskiy, Eylon Caspi, Randy Huang, Joseph Yeh, Michael Chu, John Wawrzynek, André DeHon
    Analysis of quasi-static scheduling techniques in a virtualized reconfigurable machine. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:196-205 [Conf]
  6. Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda
    A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:248- [Conf]
  7. Eylon Caspi, Michael Chu, Randy Huang, Joseph Yeh, John Wawrzynek, André DeHon
    Stream Computations Organized for Reconfigurable Execution (SCORE). [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:605-614 [Conf]
  8. Chao You, Jong-Ru Guo, Michael Chu, Russell P. Kraft, Bryan S. Goda, John F. McDonald
    A 11 GHz FPGA with Test Applications. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:101-105 [Conf]
  9. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Robert W. Heikaus, Okan Erdogan, Peter F. Curran, Bryan S. Goda, Kuan Zhou, John F. McDonald
    Gigahertz FPGA by SiGe BiCMOS Technology for Low Power, High Speed Computing with 3-D Memory. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:11-20 [Conf]
  10. Jong-Ru Guo, Chao You, Paul F. Curran, Michael Chu, Kuan Zhou, Jiedong Diao, A. George, Russell P. Kraft, John F. McDonald
    The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:141-144 [Conf]
  11. Chao You, Jong-Ru Guo, Russell P. Kraft, Kuan Zhou, Michael Chu, John F. McDonald
    A 5-20 GHz, low power FPGA implemented by SiGe HBT BiCMOS technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:37-40 [Conf]
  12. Jong-Ru Guo, Chao You, Michael Chu, Okan Erdogan, Russell P. Kraft, John F. McDonald
    A High Speed Reconfigurable Gate Array for Gigahertz Applications. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:124-129 [Conf]
  13. Sanjeev Kumar, Michael Chu, Christopher J. Hughes, Partha Kundu, Anthony Nguyen
    Hybrid transactional memory. [Citation Graph (0, 0)][DBLP]
    PPOPP, 2006, pp:209-220 [Conf]
  14. Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:525-540 [Journal]
  15. Allison Woodruff, Chris Olston, Alexander Aiken, Michael Chu, Vuk Ercegovac, Mark Lin, Mybrid Spalding, Michael Stonebraker
    DataSplash: A Direct Manipulation Environment for Programming Semantic Zoom Visualizations of Tabular Data. [Citation Graph (0, 0)][DBLP]
    J. Vis. Lang. Comput., 2001, v:12, n:5, pp:551-571 [Journal]
  16. André DeHon, Yury Markovskiy, Eylon Caspi, Michael Chu, Randy Huang, Stylianos Perissakis, Laura Pozzi, Joseph Yeh, John Wawrzynek
    Stream computations organized for reconfigurable execution. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2006, v:30, n:6, pp:334-354 [Journal]
  17. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Peter F. Curran, Kuan Zhou, Bryan S. Goda, John F. McDonald
    A 5-10GHz SiGe BiCMOS FPGA with new configurable logic block. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2005, v:29, n:2-3, pp:121-131 [Journal]
  18. Chao You, Jong-Ru Guo, Russell P. Kraft, Michael Chu, Bryan S. Goda, John F. McDonald
    A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1051-1054 [Journal]

  19. Amdahl's figure of merit, SiGe HBT BiCMOS, and 3D chip stacking. [Citation Graph (, )][DBLP]


  20. Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers. [Citation Graph (, )][DBLP]


  21. Scientific and Engineering Computing Using ATI Stream Technology. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002