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Renqiu Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jawad Khan, Jayanthi Rajagopalan, Renqiu Huang, Ranga Vemuri
    A Portable Face Recognition System Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    ERSA, 2004, pp:213-217 [Conf]
  2. Renqiu Huang, Tommy Cheung, Ted Kok
    A Statistical Analysis Tool for FPLD Architectures. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:1000-1003 [Conf]
  3. Renqiu Huang, Manish Handa, Ranga Vemuri
    Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2004, pp:900-905 [Conf]
  4. Renqiu Huang, Ranga Vemuri
    PAHLS: Towards Run-Time Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:739-740 [Conf]
  5. Renqiu Huang, Ranga Vemuri
    Transformation synthesis for data intensive applications to FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:349-352 [Conf]
  6. Renqiu Huang, Ranga Vemuri
    Analysis and evaluation of a hybrid interconnect structure for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:595-601 [Conf]
  7. Renqiu Huang, Ranga Vemuri
    Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  8. Renqiu Huang, Ranga Vemuri
    Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:250-251 [Conf]
  9. Renqiu Huang, Ranga Vemuri
    On-Line Synthesis for Partially Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:663-668 [Conf]

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