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Publications of Author

1. Emanuele Bottino, Sergio Martinoia, Maurizio Valle
   Integrated low noise signal conditioning interface for neuroengineering applications. [Citation Graph (0, 0)][DBLP]
   ESANN, 2004, pp:513-518 [Conf]
   
2. Davide Anguita, Maurizio Valle
   Perspectives on dedicated hardware implementations. [Citation Graph (0, 0)][DBLP]
   ESANN, 2001, pp:45-56 [Conf]
   
3. Francesco Diotalevi, Maurizio Valle
   Weight perturbation learning algorithm with local learning rate adaptation for the classification of remote-sensing images. [Citation Graph (0, 0)][DBLP]
   ESANN, 2001, pp:217-222 [Conf]
   
4. Matteo Giudici, Filippo Queirolo, Maurizio Valle
   Evaluation of gradient descent learning algorithms with adaptive and local learning rate for recognising hand-written numerals. [Citation Graph (0, 0)][DBLP]
   ESANN, 2002, pp:289-294 [Conf]
   
5. Daniela Baratta, Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle, Giovanni Canepa, Riccardo Parenti, Carla Penno
   A Hardware Implementation of Hierarchical Neural Networks for Real-Time Quality Contol Systems in Industrial Applications. [Citation Graph (0, 0)][DBLP]
   ICANN, 1997, pp:1229-1234 [Conf]
   
6. Matteo Giudici, Filippo Queirolo, Maurizio Valle
   Stochastic Supervised Learning Algorithms with Local and Adaptive Learning Rate for Recognising Hand-Written Characters. [Citation Graph (0, 0)][DBLP]
   ICANN, 2002, pp:619-624 [Conf]
   
7. Francesco Diotalevi, Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle
   Evaluation and Validation of Local and Adaptive Weight Perturbation Learning Algorithms for Optical Characters Recognition Applications. [Citation Graph (0, 0)][DBLP]
   IIA/SOCO, 1999, pp:- [Conf]
   
8. Francesco Diotalevi, Maurizio Valle, Gian Marco Bo, Daniele D. Caviglia
   A VLSI Architecture for Weight Perturbation on Chip Learning Implementation. [Citation Graph (0, 0)][DBLP]
   IJCNN (4), 2000, pp:219-226 [Conf]
   
9. Francesco Diotalevi, Maurizio Valle, Daniele D. Caviglia
   Evaluation of Gradient Descent Learning Algorithms with an Adaptive Local Rate Technique for Hierarchical Feed Forward Architectures. [Citation Graph (0, 0)][DBLP]
   IJCNN (2), 2000, pp:185-190 [Conf]
   
10. Gian Marco Bo, Daniele D. Caviglia, Maurizio Valle
    An On-Chip Learning Neural Network. [Citation Graph (0, 0)][DBLP]
    IJCNN (4), 2000, pp:66-74 [Conf]
    
11. Daniela Baratta, Francesco Diotalevi, Maurizio Valle, Daniele D. Caviglia
    Gradient Descent Learning Algorithm for Hierarchical Neural Networks: A Case Study in Industrial Quality. [Citation Graph (0, 0)][DBLP]
    IWANN (2), 1999, pp:578-587 [Conf]
    
12. Daniele D. Caviglia, Maurizio Valle, Giacomo M. Bisio
    A VLSI Module for Analog Adaptive Neural Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:177-186 [Conf]
    
13. Maurizio Valle, Francesco Diotalevi
    A dedicated very low power analog VLSI architecture for smart adaptive systems. [Citation Graph (0, 0)][DBLP]
    Appl. Soft Comput., 2004, v:4, n:3, pp:206-226 [Journal]
    
14. Maurizio Valle, Luigi Raffo, Daniele D. Caviglia, Giacomo M. Bisio
    A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant. [Citation Graph (0, 0)][DBLP]
    Real-Time Imaging, 1996, v:2, n:6, pp:361-371 [Journal]
    
15. 
    Evaluating Energy Consumption in Wireless Sensor Networks Applications. [Citation Graph (, )][DBLP]
    
    
16. 
    A VHDL-based design methodology: the design experience of a high performance ASIC chip. [Citation Graph (, )][DBLP]