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Publications of Author

1. Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
   VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications. [Citation Graph (0, 0)][DBLP]
   ESANN, 2003, pp:445-450 [Conf]
   
2. Stéphane Badel, Alexandre Schmid, Yusuf Leblebici
   Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2004, pp:780-783 [Conf]
   
3. Stéphane Badel, Yusuf Leblebici
   Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:1871-1874 [Conf]
   
4. Elizabeth J. Brauer, Ilhan Hatirnaz, Stéphane Badel, Yusuf Leblebici
   Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2006, pp:- [Conf]
   
5. Francesco Regazzoni, Stéphane Badel, Thomas Eisenbarth, Johann Großschädl, Axel Poschmann, Zeynep Toprak Deniz, Marco Macchetti, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne
   A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies. [Citation Graph (0, 0)][DBLP]
   ICSAMOS, 2007, pp:209-214 [Conf]
   
6. Ilhan Hatirnaz, Stéphane Badel, Nuria Pazos, Yusuf Leblebici, Srinivasan Murali, David Atienza, Giovanni De Micheli
   Early wire characterization for predictable network-on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
   SLIP, 2007, pp:57-64 [Conf]
   
7. Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer
   Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. [Citation Graph (0, 0)][DBLP]
   VLSI-SoC, 2006, pp:234-238 [Conf]
   
8. 
   A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions. [Citation Graph (, )][DBLP]
   
   
9. 
   ARMADILLO: A Multi-purpose Cryptographic Primitive Dedicated to Hardware. [Citation Graph (, )][DBLP]
   
   
10. 
    A Generic Standard Cell Design Methodology for Differential Circuit Styles. [Citation Graph (, )][DBLP]