The SCEAS System
Navigation Menu

Search the dblp DataBase


Philipp Häfliger: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Philipp Häfliger
    Learning a temporal code. [Citation Graph (0, 0)][DBLP]
    ESANN, 1999, pp:423-428 [Conf]
  2. Jens Petter Abrahamsen, Philipp Häfliger, Tor Sverre Lande
    A time domain winner-take-all network of integrate-and-fire neurons. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:361-364 [Conf]
  3. Mehdi Azadmehr, Jens Petter Abrahamsen, Philipp Häfliger
    A foveated AER imager chip [address event representation]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2751-2754 [Conf]
  4. Philipp Häfliger, Håvard Kolle Riis
    A multi-level static memory cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:25-28 [Conf]
  5. Håvard Kolle Riis, Philipp Häfliger
    Spike based learning with weak multi-level static memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:393-396 [Conf]
  6. Philipp Häfliger, C. Rasche
    Floating gate analog memory for parameter and variable storage in a learning silicon neuron. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:416-419 [Conf]
  7. Håvard Kolle Riis, Philipp Häfliger
    An Asynchronous 4-to-4 AER Mapper. [Citation Graph (0, 0)][DBLP]
    IWANN, 2005, pp:494-501 [Conf]
  8. Philipp Häfliger, Misha Mahowald, Lloyd Watts
    A Spike Based Learning Neuron in Analog VLSI. [Citation Graph (0, 0)][DBLP]
    NIPS, 1996, pp:692-698 [Conf]
  9. Rafael Serrano-Gotarredona, Matthias Oster, Patrick Lichtsteiner, Alejandro Linares-Barranco, R. Paz-Vicente, F. Gomez-Rodriguez, Håvard Kolle Riis, Tobi Delbrück, Shih-Chii Liu, S. Zahnd, Adrian M. Whatley, Rodney J. Douglas, Philipp Häfliger, Gabriel Jiménez-Moreno, Antón Civit, Teresa Serrano-Gotarredona, A. Acosta-Jimenez, Bernabé Linares-Barranco
    AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems. [Citation Graph (0, 0)][DBLP]
    NIPS, 2005, pp:- [Conf]
  10. Hans Kristian Otnes Berge, Philipp Häfliger
    High-Speed Serial AER on FPGA. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:857-860 [Conf]

Search in 0.003secs, Finished in 0.004secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002