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Tsutomu Yoshinaga: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa
    Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:340-349 [Conf]
  2. Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba
    A Scalable FPGA-Based Custom Computing Machine for a Medical Image Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:307-308 [Conf]
  3. Takashi Yokota, Masamichi Nagafuchi, Yoshito Mekada, Tsutomu Yoshinaga, Kanemitsu Ootsu, Takanobu Baba
    Real-Time Medical Diagnosis on a Multiple FPGA-based System. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:1088-1091 [Conf]
  4. Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Sayuri Nakamura, Kanemitsu Ootsu, Takanobu Baba
    Recover-X: An Adaptive Router with Limited Escape Channels. [Citation Graph (0, 0)][DBLP]
    ICPADS, 2000, pp:272-279 [Conf]
  5. Tsutomu Yoshinaga, Masaya Hayashi, Maki Horita, Y. Yamaguchi, Kanemitsu Ootsu, Takanobu Baba
    A Cost and Performance Comparison for Wormhole Routers based on HDL Designs. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1998, pp:375-382 [Conf]
  6. Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
    Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2006, pp:345-352 [Conf]
  7. Kanemitsu Ootsu, Tsutomu Yoshinaga, Takanobu Baba
    Design and Evaluation of Speculative Multi-threading with Selective Multi-Path Execution. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:139- [Conf]
  8. Lawrence Mutenda, Manabu Hiyama, Tsutomu Yoshinaga, Takanobu Baba
    Parallel Navigation in an A-NETL Based Parallel OODBMS. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1997, pp:305-316 [Conf]
  9. Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa
    On the Design of a Register Queue Based Processor Architecture (FaRM-rq). [Citation Graph (0, 0)][DBLP]
    ISPA, 2003, pp:248-262 [Conf]
  10. Takanobu Baba, Tsutomu Yoshinaga, Takahiro Furuta
    Programming and Debugging for Massively Parallelism: The Case for a Parallel Object-Oriented Language A-NETL. [Citation Graph (0, 0)][DBLP]
    OBPDC, 1995, pp:38-58 [Conf]
  11. Ta Quoc Viet, Tsutomu Yoshinaga
    Asynchronous Parallel Programming Model for SMP Clusters. [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2005, pp:355-360 [Conf]
  12. Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga
    Proposal and Design of a Parallel Queue Processor Architecture (PQP). [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:549-554 [Conf]
  13. Takanobu Baba, Tsutomu Yoshinaga, Tohru Iijima, Yoshifumi Iwamoto, Masahiro Hamada, Mitsuru Suzuki
    A parallel object-oriented total architecture: A-NET. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:276-285 [Conf]
  14. Takanobu Baba, Yoshifumi Iwamoto, Tsutomu Yoshinaga
    A network-topology independent task allocation strategy for parallel computers. [Citation Graph (0, 0)][DBLP]
    SC, 1990, pp:878-887 [Conf]
  15. Takanobu Baba, Yasushige Furuya, Tsutomu Yoshinaga
    Event-based debugging system for a parallel object-oriented language A-NETL. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:11, pp:53-63 [Journal]
  16. Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga
    Parallel Queue Processor Architecture Based on Produced Order Computation Model. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2005, v:32, n:3, pp:217-229 [Journal]
  17. Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
    High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:1, pp:3-15 [Journal]

  18. Prediction router: Yet another low latency on-chip router architecture. [Citation Graph (, )][DBLP]


  19. Mathematical Model for Multiobjective Synthesis of NoC Architectures. [Citation Graph (, )][DBLP]


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