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Masahiro Sowa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa
    Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:340-349 [Conf]
  2. Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa
    An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. [Citation Graph (0, 0)][DBLP]
    EUC, 2005, pp:77-86 [Conf]
  3. Takaya Arita, Hiromitsu Takagi, Masahiro Sowa
    V++: An Instruction-Restructurable Processor Architecture. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:398-408 [Conf]
  4. Kirilka Nikolova, Masahiro Sowa
    Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems. [Citation Graph (0, 0)][DBLP]
    HPCS, 2002, pp:182-189 [Conf]
  5. Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
    Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. [Citation Graph (0, 0)][DBLP]
    ICPP Workshops, 2006, pp:345-352 [Conf]
  6. Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa
    On the Design of a Register Queue Based Processor Architecture (FaRM-rq). [Citation Graph (0, 0)][DBLP]
    ISPA, 2003, pp:248-262 [Conf]
  7. Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa
    On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. [Citation Graph (0, 0)][DBLP]
    ISPA Workshops, 2006, pp:37-46 [Conf]
  8. Kirilka Nikolova, Sou Pei You, Masahiro Sowa
    Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems. [Citation Graph (0, 0)][DBLP]
    PARA, 2002, pp:484-493 [Conf]
  9. Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga
    Proposal and Design of a Parallel Queue Processor Architecture (PQP). [Citation Graph (0, 0)][DBLP]
    IASTED PDCS, 2002, pp:549-554 [Conf]
  10. Mitsuaki Nakasumi, Shusuke Okamoto, Masahiro Sowa
    Program Controlled Cache Memory on Parallel Computer. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1997, pp:1423-1433 [Conf]
  11. Shusuke Okamoto, Masahiro Sowa
    Hybrid Processor Based on VLIW and PN-Superscalar. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1996, pp:623-632 [Conf]
  12. Shusuke Okamoto, Masahiro Sowa
    Intruction Fetch Mechanism for PN-Superscalar. [Citation Graph (0, 0)][DBLP]
    PDPTA, 1997, pp:1406-1410 [Conf]
  13. T. Smigelski, Tadao Murata, Masahiro Sowa
    A Timed Petri Net Model and Simulation of a Dataflow Computer. [Citation Graph (0, 0)][DBLP]
    PNPM, 1985, pp:56-63 [Conf]
  14. Soichi Shigeta, Kentaro Shimizu, Masahiro Sowa
    Access route control by an extended key/lock scheme. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 2001, v:16, n:5, pp:319-325 [Journal]
  15. Masahiro Sowa, Tadao Murata
    A Data Flow Computer Architecture with Program and Token Memories. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:9, pp:820-824 [Journal]
  16. Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga
    Parallel Queue Processor Architecture Based on Produced Order Computation Model. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2005, v:32, n:3, pp:217-229 [Journal]
  17. Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa
    High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. [Citation Graph (0, 0)][DBLP]
    The Journal of Supercomputing, 2006, v:38, n:1, pp:3-15 [Journal]

  18. An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. [Citation Graph (, )][DBLP]


  19. Mathematical Model for Multiobjective Synthesis of NoC Architectures. [Citation Graph (, )][DBLP]


  20. Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. [Citation Graph (, )][DBLP]


  21. New Code Generation Algorithm for QueueCore—An Embedded Processor with High ILP. [Citation Graph (, )][DBLP]


  22. Queue Register File Optimization Algorithm for QueueCore Processor. [Citation Graph (, )][DBLP]


  23. A new code generation algorithm for 2-offset producer order queue computation model. [Citation Graph (, )][DBLP]


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