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Neungsoo Park: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jongwoo Bae, Neungsoo Park, Seong-Won Lee
    Register Array Structure for Effective Edge Filtering Operation of Deblocking Filter. [Citation Graph (0, 0)][DBLP]
    EUC, 2006, pp:805-813 [Conf]
  2. Myungho Lee, Yeonseung Ryu, Tae-Sun Chung, Neungsoo Park
    Performance Evaluation of a Chip-MultiThreading Server for High Performance Computing Applications. [Citation Graph (0, 0)][DBLP]
    HiPC, 2006, pp:572-582 [Conf]
  3. Eui Bong Jung, Han Wook Cho, Neungsoo Park, Yong Ho Song
    SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (4), 2006, pp:244-251 [Conf]
  4. Seong-Won Lee, Neungsoo Park, Jean-Luc Gaudiot
    Low Power Microprocessor Design for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCSA (4), 2006, pp:622-630 [Conf]
  5. Young Won Lim, Neungsoo Park, Viktor K. Prasanna
    Efficient Algorithms for Multi-dimensional Block-Cyclic Redistribution of Arrays. [Citation Graph (0, 0)][DBLP]
    ICPP, 1997, pp:234-241 [Conf]
  6. Neungsoo Park, Bo Hong, Viktor K. Prasanna
    Analysis of Memory Hierarchy Performance of Block Data Layout. [Citation Graph (0, 0)][DBLP]
    ICPP, 2002, pp:35-0 [Conf]
  7. Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Viktor K. Prasanna
    Performance of On-Chip Multiprocessors for Vision Tasks. [Citation Graph (0, 0)][DBLP]
    IPDPS Workshops, 2000, pp:242-249 [Conf]
  8. Neungsoo Park, Dongsoo Kang, Kiran Bondalapati, Viktor K. Prasanna
    Dynamic Data Layouts for Cache-Conscious Factorization of DFT. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:693-702 [Conf]
  9. Yongwha Chung, Kichul Kim, Min Kim, Sung Bum Pan, Neungsoo Park
    A Hardware Implementation for Fingerprint Retrieval. [Citation Graph (0, 0)][DBLP]
    KES (3), 2005, pp:374-380 [Conf]
  10. Janghaeng Lee, Sung Ho Hwang, Neungsoo Park, Seong-Won Lee, Sungik Jun, Young Soo Kim
    A high performance NIDS using FPGA-based regular expression matching. [Citation Graph (0, 0)][DBLP]
    SAC, 2007, pp:1187-1191 [Conf]
  11. Neungsoo Park, Bo Hong, Viktor K. Prasanna
    Tiling, Block Data Layout, and Memory Hierarchy Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:7, pp:640-654 [Journal]
  12. Neungsoo Park, Viktor K. Prasanna, Cauligi S. Raghavendra
    Efficient Algorithms for Block-Cyclic Array Redistribution Between Processor Sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:12, pp:1217-1240 [Journal]

  13. Quarter-pel Interpolation Architecture in H.264/AVC Decoder. [Citation Graph (, )][DBLP]

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