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Raphael Weber:
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Publications of Author
- Florian Dittmann, Achim Rettberg, Raphael Weber
Path Concepts for a Reconfigurable Bit-Serial Synchronous Architecture. [Citation Graph (0, 0)][DBLP] EUC, 2005, pp:448-457 [Conf]
Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture. [Citation Graph (, )][DBLP]
Optimization techniques for a reconfigurable, self-timed, and bit-serial architecture. [Citation Graph (, )][DBLP]
Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture. [Citation Graph (, )][DBLP]
Low-Level Space Optimization of an AES Implementation for a Bit-Serial Fully Pipelined Architecture. [Citation Graph (, )][DBLP]
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