Search the dblp DataBase

Publications of Author

1. Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
   Analyzing the Performance of Mesh and Fat-Tree Topologies for Network on Chip Design. [Citation Graph (0, 0)][DBLP]
   EUC, 2005, pp:300-310 [Conf]
   
2. Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
   Designing On-Chip Network Based on Optimal Latency Criteria. [Citation Graph (0, 0)][DBLP]
   ICESS, 2005, pp:287-298 [Conf]
   
3. Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
   Realization of Video Object Plane Decoder on On-Chip Network Architecture. [Citation Graph (0, 0)][DBLP]
   ICESS, 2005, pp:256-264 [Conf]
   
4. Vu-Duc Ngo, Huy Nam Nguyen, YoungHwan Bae, HanJin Cho, Hae-Wook Choi
   Throughput Aware Mapping for Network on Chip Design of H.264 Decoder. [Citation Graph (0, 0)][DBLP]
   ISPA Workshops, 2006, pp:791-802 [Conf]
   
5. Vu-Duc Ngo, Huy Nam Nguyen, Hae-Wook Choi
   The Optimum Network on Chip Architectures for Video Object Plane Decoder Design. [Citation Graph (0, 0)][DBLP]
   ISPA, 2006, pp:75-85 [Conf]
   
6. Huy Nam Nguyen, Vu-Duc Ngo, Hae-Wook Choi
   Realization of video object plane decoder on mesh on-chip network architecture. [Citation Graph (0, 0)][DBLP]
   Circuits, Signals, and Systems, 2005, pp:137-141 [Conf]
   
7. Vu-Duc Ngo, June-Young Chang, YoungHwan Bae, HanJin Cho, Hae-Wook Choi
   Latency Optimization for NoC Design of H.264 Decoder Based on Self-similar Traffic Modeling. [Citation Graph (0, 0)][DBLP]
   ISPA, 2007, pp:289-302 [Conf]
   
8. Seongmin Noh, Daehyun Kim, Vu-Duc Ngo, Hae-Wook Choi
   Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip. [Citation Graph (0, 0)][DBLP]
   ISPA, 2007, pp:268-277 [Conf]
   
9. Huy Nam Nguyen, Vu-Duc Ngo, YoungHwan Bae, HanJin Cho, Hae-Wook Choi
   An QoS Aware Mapping of Cores Onto NoC Architectures. [Citation Graph (0, 0)][DBLP]
   ISPA, 2007, pp:278-288 [Conf]