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Yuzo Takamatsu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masakatu Morii, Yuzo Takamatsu
    Exponetiation in Finite Fields Using Dual Basis Multiplier. [Citation Graph (0, 0)][DBLP]
    AAECC, 1990, pp:354-366 [Conf]
  2. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu
    Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:659-664 [Conf]
  3. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault models and test generation for IDDQ testing: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:509-514 [Conf]
  4. Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu
    Design of C-Testable Multipliers Based on the Modified Booth Algorithm. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:42-47 [Conf]
  5. Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu
    Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:46-49 [Conf]
  6. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
    A Method to Reduce Power Dissipation during Test for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:326-331 [Conf]
  7. Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita
    Test sequence compaction for sequential circuits with reset states. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:165-170 [Conf]
  8. Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita
    Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:141-146 [Conf]
  9. Yoshinobu Higami, Naoko Takahashi, Yuzo Takamatsu
    Test Generation for Double Stuck-at Faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:71-75 [Conf]
  10. Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
    Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:242-247 [Conf]
  11. Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu
    Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:222-227 [Conf]
  12. Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu
    Diagnosis of Single Gate Delay Faults in Combinational Circuits using Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:108-112 [Conf]
  13. Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Toshiyuki Matsunaga
    A Method of Generating Tests for Marginal Delays an Delay Faults in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:320-325 [Conf]
  14. Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida
    Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:341-346 [Conf]
  15. Hiroshi Takahashi, Marong Phadoongsidhi, Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu
    Simulation-Based Diagnosis for Crosstalk Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:63-0 [Conf]
  16. Hiroshi Takahashi, Takashi Watanabe, Yuzo Takamatsu
    Generation of tenacious tests for small gate delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:332-338 [Conf]
  17. Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu
    Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:216-221 [Conf]
  18. Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu
    Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:58-64 [Conf]
  19. Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
    Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:237-0 [Conf]
  20. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu
    Modifying Test Vectors for Reducing Power Dissipation in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DELTA, 2002, pp:431-433 [Conf]
  21. Hiroshi Takahashi, Yasunori Tsugaoka, Hidekazu Ayano, Yuzo Takamatsu
    BIST Based Fault Diagnosis Using Ambiguous Test Set. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:89-96 [Conf]
  22. Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
    Effective Post-BIST Fault Diagnosis for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:401-109 [Conf]
  23. Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
    Multiple Fault Diagnosis in Sequential Circuits Using Sensitizing Sequence Pairs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:86-95 [Conf]
  24. Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
    A Method to Find Don't Care Values in Test Sequences for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:397-0 [Conf]
  25. T. Seiyama, Hiroshi Takahashi, Yoshinobu Higami, Kazuo Yamazaki, Yuzo Takamatsu
    On the fault diagnosis in the presence of unknown fault models using pass/fail information. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2987-2990 [Conf]
  26. Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
    On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:568-577 [Conf]
  27. Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
    An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. [Citation Graph (0, 0)][DBLP]
    PRDC, 2002, pp:275-282 [Conf]
  28. Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu
    Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:781-786 [Conf]
  29. Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu
    General BIST-Amenable Method of Test Generation for Iterative Logic Arrays. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:171-178 [Conf]
  30. Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu
    A New Method for Diagnosing Multiple Stuck-at Faults using Multiple and Single Fault Simulations. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:64-69 [Conf]
  31. Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu
    Multiple Fault Diagnosis by Sensitizing Input Pairs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:44-52 [Journal]
  32. Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
    Test cost reduction for logic circuits: Reduction of test data volume and test application time. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2005, v:36, n:6, pp:69-83 [Journal]
  33. Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita
    Static test compaction for IDDQ testing of bridging faults in sequential circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2000, v:31, n:11, pp:41-50 [Journal]
  34. Tetsuro Minamiyama, Yuzo Takamatsu
    Identification of redundant faults in combinational circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2000, v:31, n:6, pp:65-73 [Journal]
  35. Hiroshi Takahashi, Takashi Watanabe, Toshiyuki Matsunaga, Yuzo Takamatsu
    Tests for small gate delay faults in combinational circuits and a test generation method. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:6, pp:68-76 [Journal]
  36. Hiroshi Takahashi, Kwame Osei Boateng, Kewal K. Saluja, Yuzo Takamatsu
    On diagnosing multiple stuck-at faults using multiple and singlefault simulation in combinational circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:3, pp:362-368 [Journal]
  37. Hiroshi Takahashi, Keith J. Keller, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu
    A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:252-263 [Journal]
  38. Yuzo Takamatsu, Kozo Kinoshita
    CONT: a concurrent test generation system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:966-972 [Journal]

  39. New Class of Tests for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]


  40. Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent Lines. [Citation Graph (, )][DBLP]


  41. Timing-Aware Diagnosis for Small Delay Defects. [Citation Graph (, )][DBLP]


  42. A Novel Approach for Improving the Quality of Open Fault Diagnosis. [Citation Graph (, )][DBLP]


  43. Fault Effect of Open Faults Considering Adjacent Signal Lines in a 90 nm IC. [Citation Graph (, )][DBLP]


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