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Premachandran R. Menon :
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Hitesh Ajuha , Premachandran R. Menon Delay Reduction by Segment Substitution. [Citation Graph (0, 0)][DBLP ] EDAC-ETC-EUROASIC, 1994, pp:82-86 [Conf ] Wuudiann Ke , Premachandran R. Menon Synthesis of Delay-Verifiable Two-Level Circuits. [Citation Graph (0, 0)][DBLP ] EDAC-ETC-EUROASIC, 1994, pp:297-301 [Conf ] Miron Abramovici , Premachandran R. Menon Fault simulation on reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] FCCM, 1997, pp:182-191 [Conf ] D. B. Armstrong , Arthur D. Friedman , Premachandran R. Menon Synthesis of Asynchronous Sequential Circuits with Minimum Number of Delay Elements [Citation Graph (0, 0)][DBLP ] FOCS, 1967, pp:95-105 [Conf ] C. J. Tan , Premachandran R. Menon , Arthur D. Friedman Structural Simplification and Decomposition of Asynchronous Sequential Circuits [Citation Graph (0, 0)][DBLP ] FOCS, 1968, pp:7-19 [Conf ] Wolfgang Kunz , Premachandran R. Menon Multi-level logic optimization by implication analysis. [Citation Graph (0, 0)][DBLP ] ICCAD, 1994, pp:6-13 [Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Test generation for primitive path delay faults in combinational circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:636-641 [Conf ] Ramesh C. Tekumalla , Premachandran R. Menon On primitive fault test generation in non-scan sequential circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1998, pp:275-282 [Conf ] Wuudiann Ke , Premachandran R. Menon Delay-Verifiability of Combinational Circuits Based on Primitive Faults. [Citation Graph (0, 0)][DBLP ] ICCD, 1994, pp:86-90 [Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. [Citation Graph (0, 0)][DBLP ] ICCD, 1997, pp:648-653 [Conf ] Miron Abramovici , Ytzhak H. Levendel , Premachandran R. Menon A logic simulation machine. [Citation Graph (0, 0)][DBLP ] ISCA, 1982, pp:148-157 [Conf ] P. N. Anirudhan , Premachandran R. Menon Symbolic Test Generation for Hierarchically Modeled Digital Systems. [Citation Graph (0, 0)][DBLP ] ITC, 1989, pp:461-469 [Conf ] Miron Abramovici , James J. Kulikowski , Premachandran R. Menon , David T. Miller Test Generation In Lamp2: System Overview. [Citation Graph (0, 0)][DBLP ] ITC, 1985, pp:45-48 [Conf ] Miron Abramovici , James J. Kulikowski , Premachandran R. Menon , David T. Miller Test Generation In Lamp2: Concepts and Algorithms. [Citation Graph (0, 0)][DBLP ] ITC, 1985, pp:49-56 [Conf ] Miron Abramovici , Premachandran R. Menon A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. [Citation Graph (0, 0)][DBLP ] ITC, 1983, pp:138-142 [Conf ] C. H. Chen , Premachandran R. Menon An Approach to Functional Level Testability Analysis. [Citation Graph (0, 0)][DBLP ] ITC, 1989, pp:373-380 [Conf ] Ian G. Harris , Premachandran R. Menon , Russell Tessier BIST-based delay path testing in FPGA architectures. [Citation Graph (0, 0)][DBLP ] ITC, 2001, pp:932-938 [Conf ] Bong-Hee Park , Premachandran R. Menon Robustly Scan-Testable CMOS Sequential Circuits. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:263-272 [Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Delay Testing with Clock Control: An Alternative to Enhanced Scan. [Citation Graph (0, 0)][DBLP ] ITC, 1997, pp:454-462 [Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Robust testability of primitive faults using test points. [Citation Graph (0, 0)][DBLP ] ITC, 1999, pp:260-268 [Conf ] Ramesh C. Tekumalla , Premachandran R. Menon Identifying Redundant Path Delay Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1996, pp:406-411 [Conf ] Wuudiann Ke , Premachandran R. Menon Multifault testability of delay-testable circuits. [Citation Graph (0, 0)][DBLP ] VTS, 1995, pp:400-409 [Conf ] Arthur D. Friedman , Premachandran R. Menon Design of Generalized Double Rank and Multiple Rank Sequential Circuits [Citation Graph (0, 0)][DBLP ] Information and Control, 1969, v:15, n:5, pp:436-451 [Journal ] Premachandran R. Menon On Sequential Machine Decompositions for Reducing the Number of Delay Elements [Citation Graph (0, 0)][DBLP ] Information and Control, 1969, v:15, n:3, pp:274-287 [Journal ] Miron Abramovici , Premachandran R. Menon A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1985, v:34, n:7, pp:658-663 [Journal ] Miron Abramovici , Premachandran R. Menon , David T. Miller Checkpoint Faults are not Sufficient Target Faults for Test Generation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1986, v:35, n:8, pp:769-771 [Journal ] Wuudiann Ke , Premachandran R. Menon Synthesis of Delay-Verifiable Combinational Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1995, v:44, n:2, pp:213-222 [Journal ] Ytzhak H. Levendel , Premachandran R. Menon Test Generation Algorithms for Computer Hardware Description Languages. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1982, v:31, n:7, pp:577-588 [Journal ] Gordon K. Lin , Premachandran R. Menon Totally Preset Checking Experiments for Sequential Machines. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1983, v:32, n:2, pp:101-108 [Journal ] Premachandran R. Menon , Stephen G. Chappell Deductive Fault Simulation with Functional Blocks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1978, v:27, n:8, pp:689-695 [Journal ] Ramesh C. Tekumalla , Premachandran R. Menon On Redundant Path Delay Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2000, v:49, n:3, pp:277-282 [Journal ] Miron Abramovici , Ytzhak H. Levendel , Premachandran R. Menon A Logic Simulation Machine. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:2, pp:82-94 [Journal ] Wuudiann Ke , Premachandran R. Menon Path-delay-fault testable nonscan sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:576-582 [Journal ] Wuudiann Ke , Premachandran R. Menon Delay-testable implementations of symmetric functions. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:772-775 [Journal ] Wolfgang Kunz , Dominik Stoffel , Premachandran R. Menon Logic optimization and equivalence checking by implication analysis. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:266-281 [Journal ] Premachandran R. Menon , Hitesh Ahuja , Mohan Harihara Redundancy identification and removal in combinational circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:5, pp:646-651 [Journal ] Premachandran R. Menon , Ytzhak H. Levendel , Miron Abramovici SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:6, pp:738-747 [Journal ] Premachandran R. Menon , Weifeng Xu , Russell Tessier Design-specific path delay testing in lookup-table-based FPGAs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:867-877 [Journal ] Ohyoung Song , Premachandran R. Menon Acceleration of trace-based fault simulation of combinational circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1413-1419 [Journal ] Ohyoung Song , Premachandran R. Menon 3-valued trace-based fault simulation of synchronous sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:9, pp:1419-1424 [Journal ] O. Y. Song , Bong-Hee Park , Premachandran R. Menon Divergence and scheduling in functional level concurrent fault simulation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:734-736 [Journal ] Ramesh C. Tekumalla , Premachandran R. Menon Identification of primitive faults in combinational and sequentialcircuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1426-1442 [Journal ] Search in 0.007secs, Finished in 0.286secs