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Savita Banerjee: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
    Signal Transition Graph Transformations for Initializability. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:670- [Conf]
  2. Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee
    Buffer assignment for data driven architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:665-668 [Conf]
  3. Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
    Initialization Isuues in the Synthesis of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1994, pp:447-452 [Conf]
  4. Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy
    Synchronous Test Generation Model for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:178-185 [Conf]
  5. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
    Synthesis of Initializable Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:383-388 [Conf]
  6. Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan
    Buffer Assignment Algorithms on Data Driven ASICs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:1, pp:16-32 [Journal]
  7. Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
    Synthesis of initializable asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:254-263 [Journal]

  8. Layout-aware Illinois Scan design for high fault coverage coverage. [Citation Graph (, )][DBLP]


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