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Yih-Lang Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yih-Lang Li, Cheng-Wen Wu
    Logic and Fault Simulation by Cellular Automata. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:552-556 [Conf]
  2. Jin-Yih Li, Yih-Lang Li
    An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:7-13 [Conf]
  3. Yih-Lang Li, Cheng-Wen Wu
    Cellular automata for efficient parallel logic and fault simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:740-749 [Journal]
  4. Yiming Li, Shao-Ming Yu, Yih-Lang Li
    A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (4), 2007, pp:259-266 [Conf]

  5. Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. [Citation Graph (, )][DBLP]

  6. Double patterning lithography aware gridless detailed routing with innovative conflict graph. [Citation Graph (, )][DBLP]

  7. Multi-threaded collision-aware global routing with bounded-length maze routing. [Citation Graph (, )][DBLP]

  8. GRPlacer: Improving routability and wire-length of global routing with circuit replacement. [Citation Graph (, )][DBLP]

  9. Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. [Citation Graph (, )][DBLP]

  10. Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. [Citation Graph (, )][DBLP]

  11. Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. [Citation Graph (, )][DBLP]

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