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Publications of Author

1. Roberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina
   A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 1996, pp:207-214 [Conf]
   
2. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
   Performance Analysis of Electronic Commerce Multiprocessor Server. [Citation Graph (0, 0)][DBLP]
   HICSS, 2000, pp:- [Conf]
   
3. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
   Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. [Citation Graph (0, 0)][DBLP]
   HICSS, 2001, pp:- [Conf]
   
4. Roberto Giorgi, Cosimo Antonio Prete, Gianpaolo Prina, Luigi M. Ricciardi
   A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
   HICSS (1), 1997, pp:266-275 [Conf]
   
5. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
   Process Migration Effects on Memory Performance of Multiprocessor. [Citation Graph (0, 0)][DBLP]
   HiPC, 1999, pp:133-142 [Conf]
   
6. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
   Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. [Citation Graph (0, 0)][DBLP]
   NETWORKING Workshops, 2002, pp:134-146 [Conf]
   
7. Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli
   A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. [Citation Graph (0, 0)][DBLP]
   SBAC-PAD, 2004, pp:238-245 [Conf]
   
8. Pierfrancesco Foglia, Roberto Giorgi, Cosimo Antonio Prete
   Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. [Citation Graph (0, 0)][DBLP]
   J. Parallel Distrib. Comput., 2005, v:65, n:3, pp:289-306 [Journal]
   
9. Krishna M. Kavi, Joseph Arul, Roberto Giorgi
   Execution and Cache Performance of the Scheduled Dataflow Architecture. [Citation Graph (0, 0)][DBLP]
   J. UCS, 2000, v:6, n:10, pp:948-967 [Journal]
   
10. Sandro Bartolini, Roberto Giorgi, Jelica Protic, Cosimo Antonio Prete, M. Valero
    Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:9-12 [Journal]
    
11. Irina Branovic, Roberto Giorgi, Enrico Martinelli
    A workload characterization of elliptic curve cryptography methods in embedded environments. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:27-34 [Journal]
    
12. Krishna M. Kavi, Roberto Giorgi, Joseph Arul
    Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:8, pp:834-846 [Journal]
    
13. Roberto Giorgi, Cosimo Antonio Prete
    PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1999, v:10, n:7, pp:742-763 [Journal]
    
14. Krishna M. Kavi, Joseph Arul, Roberto Giorgi
    Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications. [Citation Graph (0, 0)][DBLP]
    ISCA PDCS, 2001, pp:365-371 [Conf]
    
15. 
    Reducing Leakage through Filter Cache. [Citation Graph (, )][DBLP]
    
    
16. 
    Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. [Citation Graph (, )][DBLP]
    
    
17. 
    Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture. [Citation Graph (, )][DBLP]
    
    
18. 
    Programming Abstractions and Toolchain for Dataflow Multithreading Architectures. [Citation Graph (, )][DBLP]
    
    
19. 
    Filtering drowsy instruction cache to achieve better efficiency. [Citation Graph (, )][DBLP]
    
    
20. 
    Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. [Citation Graph (, )][DBLP]
    
    
21. 
    DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. [Citation Graph (, )][DBLP]
    
    
22. 
    Introducing Hardware TLP Support in the Cell Processor. [Citation Graph (, )][DBLP]