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Rajesh K. Bawa :
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Ludovic Jacomme , Frédéric Pétrot , Rajesh K. Bawa Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis. [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1998, pp:10317-10620 [Conf ] Rajesh K. Bawa , Emmanuelle Encrenaz A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis. [Citation Graph (0, 0)][DBLP ] FTRTFT, 1996, pp:471-474 [Conf ] Rajesh K. Bawa , S. Natesan Parallel Implementation of a Spline Based Computational Approach for Singular Perturbation Problems. [Citation Graph (0, 0)][DBLP ] HiPC, 2006, pp:254-262 [Conf ] Rajesh K. Bawa , S. Natesan Quintic Spline Based Computational Scheme for Singularly Perturbed Convection-Diffusion Problems. [Citation Graph (0, 0)][DBLP ] HPCS, 2005, pp:24-28 [Conf ] Rajesh K. Bawa , S. Natesan Uniformly Convergent Computational Technique for Singularly Perturbed Self-adjoint Mixed Boundary-Value Problems. [Citation Graph (0, 0)][DBLP ] International Conference on Computational Science (3), 2005, pp:1104-1107 [Conf ] Rajesh K. Bawa Parallelizable Computational Technique for Singularly Perturbed Boundary Value Problems Using Spline. [Citation Graph (0, 0)][DBLP ] ICCSA (1), 2006, pp:1177-1182 [Conf ] Rajesh K. Bawa , V. Rathish Kumar , Tanu Gupta Parallel Mesh Division Algorithm For General Linear Two Point Boundary Value Problems. [Citation Graph (0, 0)][DBLP ] PARELEC, 2006, pp:417-420 [Conf ] Ludovic Jacomme , Frédéric Pétrot , Rajesh K. Bawa Formal Analysis of Single WAIT VHDL processes for Semantic Based Synthesis. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1999, pp:151-156 [Conf ] Fahim Rahim-Sarwary , Emmanuelle Encrenaz , Michel Minoux , Rajesh K. Bawa Modular model checking of VLSI designs described in VHDL. [Citation Graph (0, 0)][DBLP ] Computers and Their Applications, 1998, pp:368-371 [Conf ] An Efficient Computational Technique for a System of Singularly Perturbed Initial Value Problems. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.002secs