The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Shervin Hojat: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shervin Hojat, Paul Kartschoke
    Techniques for Improving Timing Convergence of Advanced Microprocessors. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 2000, pp:1300-1306 [Conf]
  2. Shantanu Ganguly, Shervin Hojat
    Clock distribution design and verification for PowerPC microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:58-61 [Conf]
  3. Shervin Hojat, Paul Villarrubia
    An Integrated Placement and Synthesis Approach for Timing Closure of PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:206-210 [Conf]
  4. Paul Kartschoke, Shervin Hojat
    Techniques that Improved the Timing Convergence of the Gekko PowerPC Microprocessor. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:65-70 [Conf]
  5. Shervin Hojat, Richard Y. Kain
    On the simplification of a placement problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:7, pp:805-812 [Journal]

Search in 0.002secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002