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Paul Molitor: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Boris Goldengorin, Gerold Jäger, Paul Molitor
    Some Basics on Tolerances. [Citation Graph (0, 0)][DBLP]
    AAIM, 2006, pp:194-206 [Conf]
  2. Riccardo Forth, Paul Molitor
    An efficient heuristic for state encoding minimizing the BDD representations of the transistion relations of finite state machines. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:61-66 [Conf]
  3. Janett Mohnke, Paul Molitor, Sharad Malik
    Limits of using signatures for permutation independent Boolean comparison. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  4. Christoph Scholl, Paul Molitor
    Communication based FPGA synthesis for multi-output Boolean functions. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  5. Boris Goldengorin, Gerold Jäger, Paul Molitor
    Tolerance Based Contract-or-Patch Heuristic for the Asymmetric TSP. [Citation Graph (0, 0)][DBLP]
    CAAN, 2006, pp:86-97 [Conf]
  6. Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof
    Hierarchical Design Based on a Calculus of Nets. [Citation Graph (0, 0)][DBLP]
    DAC, 1987, pp:649-653 [Conf]
  7. Laura Heinrich-Litan, Ursula Fissgus, St. Sutter, Paul Molitor, Thomas Rauber
    Modeling the Communication Behavior of Distributed Memory Machines by Genetic Programming. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 1998, pp:273-278 [Conf]
  8. Jörg Ritter, Paul Molitor
    A pipelined architecture for partitioned DWT based lossy image compression using FPGA's. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:201-206 [Conf]
  9. Wolfgang Günther, Robby Schönfeld, Bernd Becker, Paul Molitor
    k-Layer Straightline Crossing Minimization by Speeding Up Sifting. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 2000, pp:253-258 [Conf]
  10. Christian Matuszewski, Robby Schönfeld, Paul Molitor
    Using Sifting for k -Layer Straightline Crossing Minimization. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 1999, pp:217-224 [Conf]
  11. Günter Hotz, Reiner Kolla, Paul Molitor
    On Network Algebras and Recursive Equations. [Citation Graph (0, 0)][DBLP]
    Graph-Grammars and Their Application to Computer Science, 1986, pp:250-261 [Conf]
  12. Laura Heinrich-Litan, Paul Molitor, Dirk Möller
    Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:126-0 [Conf]
  13. Ines Peters, Paul Molitor
    Priority driven channel pin assignment. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:132-0 [Conf]
  14. Sandro Wefel, Paul Molitor
    Prove that a faulty multiplier is faulty!? [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:43-46 [Conf]
  15. Tolga Asveren, Paul Molitor
    New Crossover Methods For Sequencing Problems. [Citation Graph (0, 0)][DBLP]
    PPSN, 1996, pp:290-299 [Conf]
  16. Michael Kaufmann, Paul Molitor, Wolfgang Vogelgesang
    Performance Driven k-Layer Wiring. [Citation Graph (0, 0)][DBLP]
    STACS, 1992, pp:489-500 [Conf]
  17. Paul Molitor
    On the Contact-Minimization-Problem. [Citation Graph (0, 0)][DBLP]
    STACS, 1987, pp:420-431 [Conf]
  18. Paul Molitor, Uwe Sparmann, Dorothea Wagner
    Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already Generated. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:149-154 [Conf]
  19. Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor
    Polynomial Formal Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:150-157 [Conf]
  20. Changxing Dong, Paul Molitor
    What Graphs can be Efficiently Represented by BDDs? [Citation Graph (0, 0)][DBLP]
    ICCTA, 2007, pp:128-134 [Conf]
  21. Paul Molitor
    A Survey on Wiring. [Citation Graph (0, 0)][DBLP]
    Elektronische Informationsverarbeitung und Kybernetik, 1991, v:27, n:1, pp:3-19 [Journal]
  22. Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor
    Polynomial Formal Verification of Multipliers. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2003, v:22, n:1, pp:39-58 [Journal]
  23. Janett Mohnke, Paul Molitor, Sharad Malik
    Limits of Using Signatures for Permutation Independent Boolean Comparison. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:2, pp:167-191 [Journal]
  24. Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor
    Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil I. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1986, v:1, n:1, pp:38-47 [Journal]
  25. Günter Hotz, Bernd Becker, Reiner Kolla, Paul Molitor
    Ein logisch-topologischer Kalkül zur Konstruktion integrierter Schaltkreise, Teil II. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1986, v:1, n:2, pp:72-82 [Journal]
  26. Janett Mohnke, Paul Molitor, Sharad Malik
    Establishing latch correspondence for sequential circuits using distinguishing signatures. [Citation Graph (0, 0)][DBLP]
    Integration, 1999, v:27, n:1, pp:33-46 [Journal]
  27. Paul Molitor
    Gutachter 2004. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2004, v:46, n:6, pp:360-0 [Journal]
  28. Paul Molitor
    Gutachter 2005. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2005, v:47, n:6, pp:366-0 [Journal]
  29. Heinz Zemanek, Johannes Oldenbourg, Paul Molitor, Klaus Küspert, Kurt Rothermel
    Zum neuen Jahrgang. [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2003, v:45, n:1, pp:3-5 [Journal]
  30. Janett Mohnke, Paul Molitor, Sharad Malik
    Application of BDDs in Boolean matching techniques for formal logic combinational verification. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:2, pp:207-216 [Journal]
  31. Laura Heinrich-Litan, Paul Molitor
    Least Upper Bounds for the Size of OBDDs Using Symmetry Properties. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:4, pp:360-368 [Journal]
  32. Bernd Becker, Rolf Drechsler, Paul Molitor
    On the generation of area-time optimal testable adders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:9, pp:1049-1066 [Journal]
  33. Paul Molitor
    Constrained via minimization for systolic arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:5, pp:537-542 [Journal]
  34. Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler
    BDD minimization using symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:81-100 [Journal]
  35. Paul Molitor
    ...was wird mit übrigens? [Citation Graph (0, 0)][DBLP]
    it - Information Technology, 2006, v:48, n:4, pp:247- [Journal]

  36. Effective Tour Searching for TSP by Contraction of Pseudo Backbone Edges. [Citation Graph (, )][DBLP]


  37. Finding Good Tours for Huge Euclidean TSP Instances by Iterative Backbone Contraction. [Citation Graph (, )][DBLP]


  38. Improving the Efficiency of Helsgaun's Lin-Kernighan Heuristic for the Symmetric TSP. [Citation Graph (, )][DBLP]


  39. Minimizing ROBDD sizes of incompletely specified Boolean functionsby exploiting strong symmetries. [Citation Graph (, )][DBLP]


  40. A graphical system for hierarchical specifications and checkups of VLSI circuits. [Citation Graph (, )][DBLP]


  41. Algorithms and Experimental Study for the Traveling Salesman Problem of Second Order. [Citation Graph (, )][DBLP]


  42. What are the samples for learning efficient routing heuristics? [MCM routing]. [Citation Graph (, )][DBLP]


  43. Effective Heuristics for Large Euclidean TSP Instances Based on Pseudo Backbones. [Citation Graph (, )][DBLP]


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