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Publications of Author

1. A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble
   Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces. [Citation Graph (0, 0)][DBLP]
   EUROMICRO, 1997, pp:409-0 [Conf]
   
2. Julien Sébot, Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
   A Parallel Algorithm for 3D Geometry Transformations in OpenGL. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 1999, pp:659-662 [Conf]
   
3. Claude Limousin, Alexis Vartanian, Jean-Luc Béchennec
   PopSPY: A PowerPC Instrumentation Tool for Multiprocessor Simulation. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 1999, pp:262-265 [Conf]
   
4. Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
   Two Schemes to Improve the Performance of a Sort-Last 3D Parallel Rendering Machine with Texture Caches. [Citation Graph (0, 0)][DBLP]
   Euro-Par, 1999, pp:757-760 [Conf]
   
5. Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
   The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches. [Citation Graph (0, 0)][DBLP]
   HPCA, 2000, pp:399-408 [Conf]
   
6. Franck Cappello, Jean-Luc Béchennec, Franck Delaplace, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
   Balanced Distributed Memory Parallel Computers. [Citation Graph (0, 0)][DBLP]
   ICPP, 1993, pp:72-76 [Conf]
   
7. Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam
   Evaluation of High Performance Multicache Parallel Texture Mapping. [Citation Graph (0, 0)][DBLP]
   International Conference on Supercomputing, 1998, pp:289-296 [Conf]
   
8. Pascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec, He Hé
   The Database Processor 'RAPID'. [Citation Graph (0, 0)][DBLP]
   IWDM, 1987, pp:171-187 [Conf]
   
9. F. Capello, Jean-Luc Béchennec, Franck Delaplace, Damien Gautier de Lahaut, Cécile Germain, Jean-Louis Giavitto, Vincent Néri, Daniel Etiemble
   A Parralel Architecture Based on Compiled Communication Schemes. [Citation Graph (0, 0)][DBLP]
   PARCO, 1993, pp:371-378 [Conf]
   
10. Franck Cappello, Jean-Luc Béchennec, Jean-Louis Giavitto
    PTAH: Introduction to a New Parallel Architecture for Highly Numeric Processing. [Citation Graph (0, 0)][DBLP]
    PARLE, 1992, pp:81-96 [Conf]
    
11. Cécile Germain, Jean-Luc Béchennec, Daniel Etiemble, Jean-Paul Sansonnet
    A Communication Architecture for a Massively Parallel Message-Passing Multicomputer. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1993, v:19, n:4, pp:338-348 [Journal]
    
12. Nathalie Drach, Jean-Luc Béchennec, Olivier Temam
    Increasing hardware data prefetching performance using the second-level cache. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2002, v:48, n:4-5, pp:137-149 [Journal]
    
13. Jean-Luc Béchennec, Mikael Briday, Sébastien Faucou, Yvon Trinquet
    Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification. [Citation Graph (0, 0)][DBLP]
    ETFA, 2006, pp:62-69 [Conf]
    
14. 
    Instruction set simulator generation using HARMLESS, a new hardware architecture description language. [Citation Graph (, )][DBLP]
    
    
15. 
    Simulator generation using an automaton based pipeline model for timing analysis. [Citation Graph (, )][DBLP]