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Zachary K. Baker:
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Publications of Author
- Zachary K. Baker, Viktor K. Prasanna
Performance Modeling and Interpretive Simulation of PIM Architectures and Applications (Research Note). [Citation Graph (0, 0)][DBLP] Euro-Par, 2002, pp:157-161 [Conf]
- Zachary K. Baker, Viktor K. Prasanna
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP] FCCM, 2004, pp:135-144 [Conf]
- Zachary K. Baker, Viktor K. Prasanna
Efficient Hardware Data Mining with the Apriori Algorithm on FPGAs. [Citation Graph (0, 0)][DBLP] FCCM, 2005, pp:3-12 [Conf]
- Zachary K. Baker, Viktor K. Prasanna
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP] FCCM, 2006, pp:67-75 [Conf]
- Zachary K. Baker, Viktor K. Prasanna
Time and area efficient pattern matching on FPGAs. [Citation Graph (0, 0)][DBLP] FPGA, 2004, pp:223-232 [Conf]
- Zachary K. Baker
Efficient FPGA-Based Security Kernels. [Citation Graph (0, 0)][DBLP] FPL, 2004, pp:1191- [Conf]
- Zachary K. Baker, Viktor K. Prasanna
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 2004, pp:311-321 [Conf]
- Hong-Jip Jung, Zachary K. Baker, Viktor K. Prasanna
Performance of FPGA implementation of bit-split architecture for intrusion detection systems. [Citation Graph (0, 0)][DBLP] IPDPS, 2006, pp:- [Conf]
- Zachary K. Baker, Viktor K. Prasanna
High-throughput linked-pattern matching for intrusion detection systems. [Citation Graph (0, 0)][DBLP] ANCS, 2005, pp:193-202 [Conf]
- Zachary K. Baker, Viktor K. Prasanna
Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP] IEEE Trans. Dependable Sec. Comput., 2006, v:3, n:4, pp:289-300 [Journal]
- Zachary K. Baker, Viktor K. Prasanna
A computationally efficient engine for flexible intrusion detection. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:10, pp:1179-1189 [Journal]
- Zachary K. Baker, Viktor K. Prasanna, Hong-Jip Jung
Regular Expression Software Deceleration for Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP] FPL, 2006, pp:1-8 [Conf]
Gradient Run-length Data Compression for Real-time Airborne Image Processing. [Citation Graph (, )][DBLP]
Matched Filter Computation on FPGA, Cell and GPU. [Citation Graph (, )][DBLP]
On the Acceleration of Shortest Path Calculations in Transportation Networks. [Citation Graph (, )][DBLP]
In-situ FPGA Debug Driven by On-Board Microcontroller. [Citation Graph (, )][DBLP]
Rotationally invariant sparse patch matching on GPU and FPGA. [Citation Graph (, )][DBLP]
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