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Yan Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Qiang Li, Yan Lin, Kun Liu, Jiubin Ju
    Constructing Correlations in Attack Connection Chains Using Active Perturbation. [Citation Graph (0, 0)][DBLP]
    AAIM, 2005, pp:252-260 [Conf]
  2. Yan Lin, Fei Li, Lei He
    Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:645-650 [Conf]
  3. Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
    Device and architecture co-optimization for FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:915-920 [Conf]
  4. Yu Hu, Yan Lin, Lei He, Tim Tuan
    Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:478-483 [Conf]
  5. Fei Li, Yan Lin, Lei He
    FPGA power reduction using configurable dual-Vdd. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:735-740 [Conf]
  6. Yan Lin, Lei He
    Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:720-725 [Conf]
  7. Yan Lin, Marek J. Druzdzel
    Relevance-Based Sequential Evidence Processing in Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    FLAIRS Conference, 1998, pp:446-450 [Conf]
  8. Fei Li, Yan Lin, Lei He, Jason Cong
    Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:42-50 [Conf]
  9. Yan Lin, Fei Li, Lei He
    Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:199-207 [Conf]
  10. Yan Lin, Lei He
    Stochastic physical synthesis for FPGAs with pre-routing interconnect uncertainty and process variation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2007, pp:80-88 [Conf]
  11. Fei Li, Yan Lin, Lei He
    Vdd programmability to reduce FPGA interconnect power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:760-765 [Conf]
  12. Ho-Yan Wong, Lerong Cheng, Yan Lin, Lei He
    FPGA device and architecture evaluation considering process variations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:19-24 [Conf]
  13. Yan Lin, Yu Hu, Lei He, Vijay Raghunat
    An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:168-173 [Conf]
  14. Anna Scaglione, Yan Lin, Georgios B. Giannakis
    Block redundant constant modulus algorithm for channel-irrespective blind identifiability. [Citation Graph (0, 0)][DBLP]
    NSIP, 1999, pp:694-698 [Conf]
  15. Yan Lin, Marek J. Druzdzel
    Computational Advantages of Relevance Reasoning in Bayesian Belief Networks. [Citation Graph (0, 0)][DBLP]
    UAI, 1997, pp:342-350 [Conf]
  16. Yan Lin, Marek J. Druzdzel
    Relevance-Based Incremental Belief Updating in Bayesian Networks. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1999, v:13, n:2, pp:285-295 [Journal]
  17. Yan Lin, Lei He
    Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2023-2034 [Journal]
  18. Xiangui Kang, Jiwu Huang, Yun Q. Shi, Yan Lin
    A DWT-DFT composite watermarking scheme robust to both affine transform and JPEG compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2003, v:13, n:8, pp:776-786 [Journal]
  19. Yan Lin, Fei Li, Lei He
    Circuits and architectures for field programmable gate array with configurable supply voltage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:9, pp:1035-1047 [Journal]
  20. Yan Lin, Lei He
    Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:636-641 [Conf]
  21. Mike Hutton, Yan Lin, Lei He
    Placement and Timing for FPGAs Considering Variations. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-7 [Conf]

  22. Trace-based framework for concurrent development of process and FPGA architecture considering process variation and reliability. [Citation Graph (, )][DBLP]


  23. Device and architecture concurrent optimization for FPGA transient soft error rate. [Citation Graph (, )][DBLP]


  24. Study on semi-finished Ship structural components assembly sequence optimization. [Citation Graph (, )][DBLP]


  25. A Logical Method of Formalization for Granular Computing. [Citation Graph (, )][DBLP]


  26. Researches on Granular Reasoning based on Granular Space. [Citation Graph (, )][DBLP]


  27. Short-Term Electricity Price Forecasting Based on Rough Sets and Improved SVM. [Citation Graph (, )][DBLP]


  28. Research on the Electric Power Enterprise Performance Evaluation Based on Symbiosis Theory. [Citation Graph (, )][DBLP]


  29. Passivity and feedback design of nonlinear stochastic systems. [Citation Graph (, )][DBLP]


  30. Smarter clustering methods for SNP genotype calling. [Citation Graph (, )][DBLP]


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