The SCEAS System
Navigation Menu

Search the dblp DataBase


Sangyeun Cho: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sangyeun Cho, Gyungho Lee
    Reducing Coherence Overhead in Shared-Bus Multiprocessors. [Citation Graph (0, 0)][DBLP]
    Euro-Par, Vol. II, 1996, pp:492-497 [Conf]
  2. Sangyeun Cho
    I-cache multi-banking and vertical interleaving. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:14-19 [Conf]
  3. Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong
    A Low-Power Cache Design for CalmRISCTM-Based Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:394-399 [Conf]
  4. Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney
    Global Bus Design of a Bus-Based COMA Multiprocessor DICE. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:231-0 [Conf]
  5. Sangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia Zheng, Stephen J. Schwinn, Xin Wang, Qing Zhao, Zhiyuan Li, David J. Lilja, Pen-Chung Yew
    High-Level Information - An Approach for Integrating Front-End and Back-End Compilers. [Citation Graph (0, 0)][DBLP]
    ICPP, 1998, pp:346-355 [Conf]
  6. Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
    Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:100-110 [Conf]
  7. Lei Jin, Sangyeun Cho
    Reducing cache traffic and energy with macro data load. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:147-150 [Conf]
  8. Choongyeun Cho, Daeik Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski
    A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:699-702 [Conf]
  9. Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
    Performance of Graceful Degradation for Cache Faults. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:409-415 [Conf]
  10. Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
    Access Region Locality for High-Bandwidth Processor Memory System Design. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:136-146 [Conf]
  11. Sangyeun Cho, Lei Jin
    Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:455-468 [Conf]
  12. Sangyeun Cho, Jinseok Kong, Gyungho Lee
    Coherence and Replacement Protocol of DICE-A Bus-Based COMA Multiprocessor. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1999, v:57, n:1, pp:14-32 [Journal]
  13. Sangyeun Cho, Pen-Chung Yew, Gyungho Lee
    A High-Bandwidth Memory Pipeline for Wide Issue Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:7, pp:709-723 [Journal]
  14. Sangyeun Cho, Lei Jin, Kiyeon Lee
    Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 2007, pp:3-11 [Conf]

  15. A flexible data to L2 cache mapping approach for future multicore processors. [Citation Graph (, )][DBLP]

  16. SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. [Citation Graph (, )][DBLP]

  17. ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors. [Citation Graph (, )][DBLP]

  18. An Efficient Hardware-Based Multi-hash Scheme for High Speed IP Lookup. [Citation Graph (, )][DBLP]

  19. Exploring the interplay of yield, area, and performance in processor caches. [Citation Graph (, )][DBLP]

  20. Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches. [Citation Graph (, )][DBLP]

  21. TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. [Citation Graph (, )][DBLP]

  22. Dynamic cache clustering for chip multiprocessors. [Citation Graph (, )][DBLP]

  23. CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. [Citation Graph (, )][DBLP]

  24. Accurately approximating superscalar processor performance from traces. [Citation Graph (, )][DBLP]

  25. Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance. [Citation Graph (, )][DBLP]

  26. CHAP: Enabling Efficient Hardware-Based Multiple Hash Schemes for IP Lookup. [Citation Graph (, )][DBLP]

Search in 0.003secs, Finished in 0.004secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002