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Resit Sendag: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Peng-fei Chuang, Resit Sendag, David J. Lilja
    Improving Data Cache Performance via Address Correlation: An Upper Bound Study. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2004, pp:541-550 [Conf]
  2. Resit Sendag, David J. Lilja, Steven R. Kunkel
    Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:468-480 [Conf]
  3. Joshua J. Yi, Resit Sendag, David J. Lilja
    Increasing Instruction-Level Parallelism with Instruction Precomputation (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2002, pp:481-485 [Conf]
  4. Joshua J. Yi, Sreekumar V. Kodakara, Resit Sendag, David J. Lilja, Douglas M. Hawkins
    Characterizing and Comparing Prevailing Simulation Techniques. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:266-277 [Conf]
  5. Keqiang Wu, Resit Sendag, David J. Lilja
    Exploring Memory Access Regularity in Pointer-Intensive Application Programs. [Citation Graph (0, 0)][DBLP]
    IDEAL, 2003, pp:472-476 [Conf]
  6. Ying Chen, Resit Sendag, David J. Lilja
    Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:76- [Conf]
  7. Resit Sendag, A. Yilmazer, Joshua J. Yi, Augustus K. Uht
    Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  8. Emre Özer, Resit Sendag, David Gregg
    Multiple-Valued Caches for Power-Efficient Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISMVL, 2005, pp:126-131 [Conf]
  9. Resit Sendag, Peng-fei Chuang, David J. Lilja
    Address Correlation: Exceeding the Limits of Locality. [Citation Graph (0, 0)][DBLP]
    Computer Architecture Letters, 2003, v:2, n:, pp:- [Journal]
  10. Resit Sendag, Ying Chen, David J. Lilja
    The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:3, pp:271-285 [Journal]
  11. Joshua J. Yi, Resit Sendag, Lieven Eeckhout, Ajay Joshi, David J. Lilja, Lizy Kurian John
    Evaluating Benchmark Subsetting Approaches. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:93-104 [Conf]
  12. Joshua J. Yi, Resit Sendag, David J. Lilja, Douglas M. Hawkins
    Speed versus Accuracy Trade-Offs in Microarchitectural Simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:11, pp:1549-1563 [Journal]

  13. Low power/area branch prediction using complementary branch predictors. [Citation Graph (, )][DBLP]

  14. An analysis of hard to predict branches. [Citation Graph (, )][DBLP]

  15. Adaptive simulation sampling using an Autoregressive framework. [Citation Graph (, )][DBLP]

  16. Branch Misprediction Prediction: Complementary Branch Predictors. [Citation Graph (, )][DBLP]

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