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Matthew K. Farrens: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kevin D. Rich, Matthew K. Farrens
    The Decoupled-Style Prefetch Architecture (Research Note). [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:989-993 [Conf]
  2. Kevin D. Rich, Matthew K. Farrens
    Code Partitioning in Decoupled Compilers. [Citation Graph (0, 0)][DBLP]
    Euro-Par, 2000, pp:1008-1017 [Conf]
  3. Michael Haungs, Phil Sallee, Matthew K. Farrens
    Branch Transition Rate: A New Metric for Improved Branch Classification Analysis. [Citation Graph (0, 0)][DBLP]
    HPCA, 2000, pp:241-250 [Conf]
  4. Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens
    Utilizing Reuse Information in Data Cache Management. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1998, pp:449-456 [Conf]
  5. Matthew K. Farrens, Arvin Park, Allison Woodruff
    CCHIME: A Cache Coherent Hybrid Interconnected Memory Extension. [Citation Graph (0, 0)][DBLP]
    IPPS, 1992, pp:573-577 [Conf]
  6. Matthew K. Farrens, Andrew R. Pleszkun
    Improving Performance of Small On-Chip Instruction Caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:234-241 [Conf]
  7. Matthew K. Farrens, Arvin Park
    Dynamic Base Register Caching: A Technique for Reducing Address Bus Width. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:128-137 [Conf]
  8. Matthew K. Farrens, Andrew R. Pleszkun
    Strategies for Achieving Improved Processor Throughput. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:362-369 [Conf]
  9. Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun
    A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1994, pp:338-347 [Conf]
  10. Mark Oskin, Frederic T. Chong, Matthew K. Farrens
    HLS: combining statistical and symbolic simulation to guide microprocessor designs. [Citation Graph (0, 0)][DBLP]
    ISCA, 2000, pp:71-82 [Conf]
  11. Jeffrey C. Becker, Arvin Park, Matthew K. Farrens
    An Analysis of the Information Content of Address Reference Streams. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:19-24 [Conf]
  12. Matthew K. Farrens, Pius Ng, Phil Nico
    A comparision of superscalar and decoupled access/execute architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:100-103 [Conf]
  13. Matthew K. Farrens, Andrew R. Pleszkun
    An evaluation of functional unit lengths for single-chip processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:209-215 [Conf]
  14. Matthew K. Farrens, Arvin Park
    Workload and Implementation Considerations for Dynamic Base Register Caching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:62-68 [Conf]
  15. Matthew K. Farrens, Arvin Park, Gary S. Tyson
    Modifying VM hardware to reduce address pin requirements. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:210-213 [Conf]
  16. Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
    Eager writeback - a technique for improving bandwidth utilization. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:11-21 [Conf]
  17. Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra
    Exploiting ILP in Page-based Intelligent Memory. [Citation Graph (0, 0)][DBLP]
    MICRO, 1999, pp:208-218 [Conf]
  18. Arvin Park, Matthew K. Farrens
    Address compression through base register caching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1990, pp:193-199 [Conf]
  19. Gary S. Tyson, Matthew K. Farrens
    Techniques for extracting instruction level parallelism on MIMD architectures. [Citation Graph (0, 0)][DBLP]
    MICRO, 1993, pp:128-137 [Conf]
  20. Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun
    A modified approach to data cache management. [Citation Graph (0, 0)][DBLP]
    MICRO, 1995, pp:93-103 [Conf]
  21. Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun
    MISC: a Multiple Instruction Stream Computer. [Citation Graph (0, 0)][DBLP]
    MICRO, 1992, pp:193-196 [Conf]
  22. Matthew K. Farrens, Brad Wetmore, Allison Woodruff
    Alleviation of tree saturation in multistage interconnection networks. [Citation Graph (0, 0)][DBLP]
    SC, 1991, pp:400-409 [Conf]
  23. Matthew K. Farrens, Andrew R. Pleszkun
    Implementation of the PIPE Processor. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1991, v:24, n:1, pp:65-69 [Journal]
  24. Matthew K. Farrens
    Distributed Decentralized Computing. [Citation Graph (0, 0)][DBLP]
    ACM Comput. Surv., 1996, v:28, n:4es, pp:28- [Journal]
  25. Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens
    Improving Bandwidth Utilization using Eager Writeback. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
  26. Mark Oskin, Frederic T. Chong, Matthew K. Farrens
    Using Statistical and Symbolic Simulation for Microprocessor Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2002, v:4, n:, pp:- [Journal]

  27. Design and evaluation of an optical CPU-DRAM interconnect. [Citation Graph (, )][DBLP]


  28. Techniques for increasing effective data bandwidth. [Citation Graph (, )][DBLP]


  29. Performance Evaluation of a Multicore System with Optically Connected Memory Modules. [Citation Graph (, )][DBLP]


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