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Author:
Zhiying Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jianjun Guo, Kui Dai, Yun Cheng, Zhiying Wang
    Research on Fast Block Participation Mode Selection Algorithm in H.264. [Citation Graph (0, 0)][DBLP]
    ACIS-ICIS, 2005, pp:111-113 [Conf]
  2. Lei Wang, Zhiying Wang, Kui Dai
    An Approximate Method for Performance Evaluation of Asynchronous Pipeline Rings. [Citation Graph (0, 0)][DBLP]
    CIT, 2006, pp:244- [Conf]
  3. Wei Chen, Rui Gong, Kui Dai, Fang Liu, Zhiying Wang
    Two New Space-Time Triple Modular Redundancy Techniques for Improving Fault Tolerance of Computer Systems. [Citation Graph (0, 0)][DBLP]
    CIT, 2006, pp:175- [Conf]
  4. Jianjun Guo, Kui Dai, Zhiying Wang
    A Heterogeneous Multi-core Processor Architecture for High Performance Computing. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:359-365 [Conf]
  5. Lei Wang, Hongyi Lu, Kui Dai, Zhiying Wang
    TengYue-1TengYue: In Chinese means jump over.: A High Performance Embedded SoC. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2004, pp:126-136 [Conf]
  6. Lei Wang, Zhiying Wang, Kui Dai
    Cycle Period Analysis and Optimization of Timed Circuits. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2006, pp:502-508 [Conf]
  7. Jingbin An, Yan Jia, Zhiying Wang
    Implementing Component Persistence in CCM Based on StarPSS. [Citation Graph (0, 0)][DBLP]
    APPT, 2005, pp:226-233 [Conf]
  8. Li Shen, Zhiying Wang, Jianzhuang Lu
    Predicate Analysis Based on Path Information. [Citation Graph (0, 0)][DBLP]
    APPT, 2003, pp:147-151 [Conf]
  9. Chenlin Huang, Huaping Hu, Zhiying Wang
    A Dynamic Trust Model Based on Feedback Control Mechanism for P2P Applications. [Citation Graph (0, 0)][DBLP]
    ATC, 2006, pp:312-321 [Conf]
  10. Fang Liu, Kui Dai, Zhiying Wang
    Improving Security Architecture Development Based on Multiple Criteria Decision Making. [Citation Graph (0, 0)][DBLP]
    AWCC, 2004, pp:214-218 [Conf]
  11. Yun Cheng, Kui Dai, Zhiying Wang, Jianjun Guo
    A Fast Motion Estimation Algorithm Based on Diamond and Simplified Square Search Patterns. [Citation Graph (0, 0)][DBLP]
    CIARP, 2005, pp:440-449 [Conf]
  12. Yuan-man Tong, Zhiying Wang, Kui Dai, Hongyi Lu
    Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor Using WDDL and Wave-Pipelining. [Citation Graph (0, 0)][DBLP]
    Inscrypt, 2006, pp:66-77 [Conf]
  13. Wei Chen, Rui Gong, Fang Liu, Kui Dai, Zhiying Wang
    Improving the Fault Tolerance of a Computer System with Space-Time Triple Modular Redundancy. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:183-190 [Conf]
  14. Hong Yue, Kui Dai, Zhiying Wang
    A Dual-core Embedded System-on-Chip Architecture for Multimedia Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:100-104 [Conf]
  15. Xue-mi Zhao, Zhiying Wang
    Power Optimization of Interconnection Networks for Transport Triggered Architecture. [Citation Graph (0, 0)][DBLP]
    ESA, 2006, pp:154-159 [Conf]
  16. Gong Rui, Chen Wei, Liu Fang, Dai Kui, Wang Zhiying
    Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:184-196 [Conf]
  17. Fangyong Hou, Zhiying Wang, Yuhua Tang, Jifeng Liu
    Verify Memory Integrity Basing on Hash Tree and MAC Combined Approach. [Citation Graph (0, 0)][DBLP]
    EUC, 2004, pp:869-878 [Conf]
  18. Fangyong Hou, Zhiying Wang, Zhen Liu, Yun Liu
    Avoid Powerful Tampering by Malicious Host. [Citation Graph (0, 0)][DBLP]
    GCC (1), 2003, pp:907-915 [Conf]
  19. Chenlin Huang, Huaping Hu, Zhiying Wang
    Modeling Time-Related Trust. [Citation Graph (0, 0)][DBLP]
    GCC Workshops, 2004, pp:382-389 [Conf]
  20. Dan Wu, Zhiying Wang, Kui Dai
    Retargetable Machine-Description System: Multi-layer Architecture Approach. [Citation Graph (0, 0)][DBLP]
    GCC, 2005, pp:1161-1166 [Conf]
  21. Hao Ren, Zhiying Wang, Zhong Liu
    A Hyper-cube based P2P Information Service for Data Grid. [Citation Graph (0, 0)][DBLP]
    GCC, 2006, pp:508-513 [Conf]
  22. Jianjun Guo, Kui Dai, Zhiying Wang
    A High Performance Heterogeneous Architecture and Its Optimization Design. [Citation Graph (0, 0)][DBLP]
    HPCC, 2006, pp:300-309 [Conf]
  23. Hong Yue, Zhiying Wang, Kui Dai
    A Heterogeneous Embedded MPSoC for Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    HPCC, 2006, pp:591-600 [Conf]
  24. Yun Cheng, Zhiying Wang, Kui Dai, Jianjun Guo
    A Fast Motion Estimation Algorithm Based on Diamond and Triangle Search Patterns. [Citation Graph (0, 0)][DBLP]
    IbPRIA (1), 2005, pp:419-426 [Conf]
  25. Kebo Wang, Zhiying Wang, Yan Jia, Weihong Han
    An Optimal Component Distribution Algorithm Based on MINLP. [Citation Graph (0, 0)][DBLP]
    ICCNMC, 2005, pp:808-816 [Conf]
  26. Ming-che Lai, Kui Dai, Li Shen, Zhiying Wang
    A New Technique for Program Code Compression in Embedded Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICESS, 2004, pp:158-164 [Conf]
  27. Fang Liu, Kui Dai, Zhiying Wang, Jun Ma
    Research on Fuzzy Group Decision Making in Security Risk Assessment. [Citation Graph (0, 0)][DBLP]
    ICN (2), 2005, pp:1114-1121 [Conf]
  28. Jing-Xin Wang, Zhiying Wang, Kui Dai
    Intrusion Alert Analysis Based on PCA and the LVQ Neural Network. [Citation Graph (0, 0)][DBLP]
    ICONIP (3), 2006, pp:217-224 [Conf]
  29. Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang
    Design of a Configurable Embedded Processor Architecture for DSP Functions. [Citation Graph (0, 0)][DBLP]
    ICPADS (2), 2005, pp:27-31 [Conf]
  30. Fangyong Hou, Zhiying Wang, Yuhua Tang, Zhen Liu
    Protecting integrity and confidentiality for data communication. [Citation Graph (0, 0)][DBLP]
    ISCC, 2004, pp:357-362 [Conf]
  31. Jing-Xin Wang, Zhiying Wang, Kui Dai
    A PCA-LVQ Model for Intrusion Alert Analysis. [Citation Graph (0, 0)][DBLP]
    ISI, 2006, pp:715-716 [Conf]
  32. Jianzhuang Lu, Chunyuan Zhang, Zhiying Wang, Yun Cheng, Dan Wu
    A Case of SCMP with TLS. [Citation Graph (0, 0)][DBLP]
    ISPA, 2004, pp:975-984 [Conf]
  33. Fangyong Hou, Hongjun He, Zhiying Wang, Kui Dai
    An Efficient Way to Build Secure Disk. [Citation Graph (0, 0)][DBLP]
    ISPEC, 2006, pp:290-301 [Conf]
  34. Fangyong Hou, Zhiying Wang, Kui Dai, Yun Liu
    Protecting Mass Data Basing on Small Trusted Agent. [Citation Graph (0, 0)][DBLP]
    ISPEC, 2005, pp:362-373 [Conf]
  35. Fangyong Hou, Zhiying Wang, Zhen Liu, Yuhua Tang, Yun Liu
    Building Efficient and Secure Communication for Grid. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2004, pp:894-900 [Conf]
  36. Fangyong Hou, Zhiying Wang, Yuhua Tang, Zhen Liu, Jin Zhou
    Protect Data Stored on Remote Server. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2004, pp:929-938 [Conf]
  37. Jiang-chun Ren, Kui Dai, Zhiying Wang
    Trust-Enhanced Alteration Scenario for Universal Computer. [Citation Graph (0, 0)][DBLP]
    PRDC, 2005, pp:275-280 [Conf]
  38. Fang Liu, Yong Chen, Kui Dai, Zhiying Wang, Zhiping Cai
    Research on Risk Probability Estimating Using Fuzzy Clustering for Dynamic Security Assessment. [Citation Graph (0, 0)][DBLP]
    RSFDGrC (2), 2005, pp:539-547 [Conf]
  39. Jiang-chun Ren, Kui Dai, Zhiying Wang, Xue-mi Zhao, Yuan-man Tong
    Design and Implementation a TPM Chip SUP320 by SOC. [Citation Graph (0, 0)][DBLP]
    SEC, 2005, pp:143-154 [Conf]
  40. GeMing Xia, Zunguo Huang, Zhiying Wang
    Secure Data Transmission on Multiple Paths in Mobile Ad Hoc Networks. [Citation Graph (0, 0)][DBLP]
    WASA, 2006, pp:424-434 [Conf]
  41. Yong Li, Lei Wang, Rui Gong, Kui Dai, Zhiying Wang
    Research and Implementation of a 32-Bit Asynchronous Multiplier. [Citation Graph (0, 0)][DBLP]
    Journal of Computer Research and Development, 2006, v:43, n:12, pp:2152-2157 [Journal]
  42. Yong Li, Zhiying Wang, Xue-mi Zhao, Jian Ruan, Kui Dai
    Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:354-363 [Conf]
  43. Gang Jin, Lei Wang, Zhiying Wang, Kui Dai
    An Optimal Design Method for De-synchronous Circuit Based on Control Graph. [Citation Graph (0, 0)][DBLP]
    APPT, 2007, pp:70-79 [Conf]
  44. Libo Huang, Li Shen, Kui Dai, Zhiying Wang
    A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design. [Citation Graph (0, 0)][DBLP]
    IEEE Symposium on Computer Arithmetic, 2007, pp:69-76 [Conf]
  45. Yong Li, Zhiying Wang, Jian Ruan, Kui Dai
    A Low-Power Globally Synchronous Locally Asynchronous FFT Processor. [Citation Graph (0, 0)][DBLP]
    HPCC, 2007, pp:168-179 [Conf]
  46. Hao Ren, Nong Xiao, Zhiying Wang
    An Interest-Based Intelligent Link Selection Algorithm in Unstructured P2P Environment. [Citation Graph (0, 0)][DBLP]
    ICA3PP, 2007, pp:326-337 [Conf]
  47. Jian Ruan, Zhiying Wang, Kui Dai, Yong Li
    Latency Estimation of the Asynchronous Pipeline Using the Max-Plus Algebra. [Citation Graph (0, 0)][DBLP]
    International Conference on Computational Science (4), 2007, pp:251-258 [Conf]
  48. Zhiying Wang, Chen He
    A minimum transmission power AM-MIMO system. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  49. Wang Jingxin, Wang Zhiying, Dai Kui
    Security Event Management System based on Mobile Agent Technology. [Citation Graph (0, 0)][DBLP]
    ISI, 2007, pp:166-171 [Conf]
  50. Miao Wang, Guiming Wu, Zhiying Wang
    Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors. [Citation Graph (0, 0)][DBLP]
    ISPA, 2007, pp:946-957 [Conf]
  51. Jian Ruan, Zhiying Wang, Kui Dai, Yong Li
    Design and Test of Self-checking Asynchronous Control Circuit. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:320-329 [Conf]
  52. Lai Mingche, Wang Zhiying, Guo Jianjun, Dai Kui, Shen Li
    Template Vertical Dictionary-Based Program Compression Scheme on the TTA. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:43-52 [Conf]
  53. Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai
    A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:216-221 [Conf]
  54. Lai Mingche, Guo Jianjun, Lv Yasuai, Dai Kui, Wang Zhiying
    The Research of an Embedded Processor Element for Multimedia Domain. [Citation Graph (0, 0)][DBLP]
    MCAM, 2007, pp:267-276 [Conf]

  55. A Low-Power Application Specific Instruction Set Processor Using Asynchronous Function Units. [Citation Graph (, )][DBLP]


  56. A Hardware Approach for Reducing Interpretation Overhead. [Citation Graph (, )][DBLP]


  57. A Dynamic Binary Translation Framework Based on Page Fault Mechanism in Linux Kernel. [Citation Graph (, )][DBLP]


  58. Dynamically utilizing computation accelerators for extensible processors in a software approach. [Citation Graph (, )][DBLP]


  59. Research on intra modes for inter-frame coding in H.264. [Citation Graph (, )][DBLP]


  60. Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques. [Citation Graph (, )][DBLP]


  61. A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. [Citation Graph (, )][DBLP]


  62. A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant Microprocessors. [Citation Graph (, )][DBLP]


  63. An Optimized COW Block Device Driver in VMM for Fast, On-Demand Software Deployment. [Citation Graph (, )][DBLP]


  64. DBTIM: An Advanced Hardware Assisted Full Virtualization Architecture. [Citation Graph (, )][DBLP]


  65. Fast, On-Demand Software Deployment with Lightweight, Independent Virtual Disk Images. [Citation Graph (, )][DBLP]


  66. SV: Enhancing SIMD Architectures via Combined SIMD-Vector Approach. [Citation Graph (, )][DBLP]


  67. An accurate and efficient performance analysis approach based on queuing model for network on chip. [Citation Graph (, )][DBLP]


  68. A Novel Data-Parallel Coprocessor for Multimedia Signal Processing. [Citation Graph (, )][DBLP]


  69. A Distributed Cut Set Discovery Algorithm in P2P Environment. [Citation Graph (, )][DBLP]


  70. Study on Key Technologies of Shipbuilding Virtual Enterprise Information Integration Oriented Agile Manufacturing. [Citation Graph (, )][DBLP]


  71. Model Driven Iterative Multi-dimensional Parallelization of Multi-task Programs for the Cell BE: A Genetic Algorithm-Based Approach. [Citation Graph (, )][DBLP]


  72. Transient Fault Tolerance on Chip Multiprocessor Based on Dual and Triple Core Redundancy. [Citation Graph (, )][DBLP]


  73. Hierarchical memory system design for a heterogeneous multi-core processor. [Citation Graph (, )][DBLP]


  74. Control flow checking and recovering based on 8051 architecture. [Citation Graph (, )][DBLP]


  75. Research of a Secure File System for Protection of Intellectual Property Right. [Citation Graph (, )][DBLP]


  76. A New CORDIC Algorithm and Software Implementation Based on Synchronized Data Triggering Architecture. [Citation Graph (, )][DBLP]


  77. Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers. [Citation Graph (, )][DBLP]


  78. Using an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia Domain. [Citation Graph (, )][DBLP]


  79. Memory System Design for a Multi-core Processor. [Citation Graph (, )][DBLP]


  80. Low-Level Component for OpenGL ES Oriented Heterogeneous Architecture with Optimization. [Citation Graph (, )][DBLP]


  81. Performance Bound Analysis and Retiming of Timed Circuits. [Citation Graph (, )][DBLP]


  82. Transient Fault Recovery on Chip Multiprocessor based on Dual Core Redundancy and Context Saving. [Citation Graph (, )][DBLP]


  83. The P2P Communication Model for a Local Memory based Multi-core Processor. [Citation Graph (, )][DBLP]


  84. A Novel Hardware Assisted Full Virtualization Technique. [Citation Graph (, )][DBLP]


  85. Implementation of OpenVG Path and Paint Algorithms on Synchronous Data Triggered Architecture with Optimization. [Citation Graph (, )][DBLP]


  86. The Design of Asynchronous Microprocessor Based on Optimized NCL_X Design-Flow. [Citation Graph (, )][DBLP]


  87. Virtual Disk Image Reclamation for Software Updates in Virtual Machine Environments. [Citation Graph (, )][DBLP]


  88. A New Description Language for Data-Driven Asynchronous Circuits and its Design Flow. [Citation Graph (, )][DBLP]


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