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Alexandre Yakovlev: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Josep Carmona, Jordi Cortadella, Victor Khomenko, Alexandre Yakovlev
    Synthesis of Asynchronous Hardware from Petri Nets. [Citation Graph (0, 0)][DBLP]
    Lectures on Concurrency and Petri Nets, 2003, pp:345-401 [Conf]
  2. Fei Xia, Fei Hao, Ian G. Clark, Alexandre Yakovlev, E. Graeme Chester
    Buffered Asynchronous Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    ACSD, 2004, pp:36-46 [Conf]
  3. Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. [Citation Graph (0, 0)][DBLP]
    ACSD, 1998, pp:152-0 [Conf]
  4. Jordi Cortadella, Kyller Costa Gorgônio, Fei Xia, Alexandre Yakovlev
    Automating Synthesis of Asynchronous Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    ACSD, 2005, pp:166-175 [Conf]
  5. Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
    Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT. [Citation Graph (0, 0)][DBLP]
    ACSD, 2004, pp:16-25 [Conf]
  6. Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
    Detecting State Coding Conflicts in STG Unfoldings Using SAT. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:51-60 [Conf]
  7. Victor Khomenko, Agnes Madalinski, Alexandre Yakovlev
    Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG Unfoldings. [Citation Graph (0, 0)][DBLP]
    ACSD, 2006, pp:57-68 [Conf]
  8. Alexander Yakovlev
    A Multi-version Data Model and Semantic-Based Transaction Processing Protocol. [Citation Graph (0, 0)][DBLP]
    ADBIS, 2005, pp:87-96 [Conf]
  9. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    Hardware and Petri Nets: Application to Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    ICATPN, 2000, pp:1-15 [Conf]
  10. Michael Kishinevsky, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Coupling Asynchrony and Interrupts: Place Chart Nets. [Citation Graph (0, 0)][DBLP]
    ICATPN, 1997, pp:328-347 [Conf]
  11. Alexandre Yakovlev
    Is the Die Cast for the Token Game? [Citation Graph (0, 0)][DBLP]
    ICATPN, 2002, pp:70-79 [Conf]
  12. Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno
    OR Causality: Modelling and Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    Application and Theory of Petri Nets, 1994, pp:568-587 [Conf]
  13. Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
    T8: Logic Design of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:26-30 [Conf]
  14. Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev
    On hazard-free implementation of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  15. Alexandre V. Bystrov, D. J. Kinniment, Alexandre Yakovlev
    Priority Arbiters. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:128-137 [Conf]
  16. Alexandre V. Bystrov, Danil Sokolov, Alexandre Yakovlev
    Low-Latency Contro Structures with Slack. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:164-173 [Conf]
  17. Alexandre V. Bystrov, Alexandre Yakovlev
    Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:127-136 [Conf]
  18. D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao
    Towards Asynchronous A-D Conversion. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1998, pp:206-215 [Conf]
  19. D. J. Kinniment, Oleh V. Maevsky, Gordon Russell, Alexandre Yakovlev, Alexandre V. Bystrov
    On-Chip Structures for Timing Measurements and Test. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:190-0 [Conf]
  20. Alex Kondratyev, Michael Kishinevsky, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev
    Technology Mapping for Speed-Independent Circuits: Decomposition and Resynthesis. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:240-253 [Conf]
  21. Fei Xia, Alexandre Yakovlev, Delong Shang, Alexandre V. Bystrov, Alexandre V. Koelmans, D. J. Kinniment
    Asynchronous Communication Mechanisms Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:150-0 [Conf]
  22. Alexandre Yakovlev, Victor Varshavsky, Vyacheslav Marakhovsky, Alexei L. Semenov
    Designing an asynchronous pipeline token ring interface. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:32-0 [Conf]
  23. Alexandre Yakovlev, Fei Xia, Delong Shang
    Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2001, pp:127-0 [Conf]
  24. Crescenzo D'Alessandro, Andrey Mokhov, Alexandre V. Bystrov, Alexandre Yakovlev
    Delay/Phase Regeneration Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:105-116 [Conf]
  25. Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Oleg V. Maevsky
    Multiple-Rail Phase-Encoding for NoC. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:107-116 [Conf]
  26. Nikolai Starodoubtsev, Sergei Bystrov, Alexandre Yakovlev
    Monotonic Circuits with Complete Acknowledgement. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:98-108 [Conf]
  27. Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno
    Partial order based approach to synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:254-0 [Conf]
  28. Danil Sokolov, Julian Murphy, Alexandre V. Bystrov, Alexandre Yakovlev
    Improving the Security of Dual-Rail Circuits. [Citation Graph (0, 0)][DBLP]
    CHES, 2004, pp:282-297 [Conf]
  29. Walter Vogler, Alexei L. Semenov, Alexandre Yakovlev
    Unfolding and Finite Prefix for Nets with Read Arcs. [Citation Graph (0, 0)][DBLP]
    CONCUR, 1998, pp:501-516 [Conf]
  30. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    Methodology and Tools for State Encoding in Asynchronous Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:63-66 [Conf]
  31. Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:110-115 [Conf]
  32. Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alexandre Yakovlev
    Basic Gate Implementation of Speed-Independent Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:56-62 [Conf]
  33. Alexei L. Semenov, Alexandre Yakovlev
    Verification of asynchronous circuits using Time Petri Net unfolding. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:59-62 [Conf]
  34. Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella
    Synthesis of Speed-Independent Circuits from STG-Unfolding Segment. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:16-21 [Conf]
  35. Frank P. Burns, Delong Shang, Albert Koelmans, Alexandre Yakovlev
    An Asynchronous Synthesis Toolset Using Verilog. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:724-725 [Conf]
  36. Alexandre V. Bystrov, Maciej Koutny, Alexandre Yakovlev
    Visualization of Partial Order Models in VLSI Design Flow. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1089- [Conf]
  37. Sohini Dasgupta, Alex Yakovlev
    Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:568-569 [Conf]
  38. Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
    Detecting State Coding Conflicts in STGs Using Integer Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:338-345 [Conf]
  39. Agnes Madalinski, Alexandre V. Bystrov, Victor Khomenko, Alexandre Yakovlev
    Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10926-10931 [Conf]
  40. Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev
    STG Optimisation in the Direct Mapping of Asynchronous Circuits . [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10932-10939 [Conf]
  41. Alexandre Yakovlev
    A Structural Technique For Fault-Protection in Asynchronous Interfaces. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:288-295 [Conf]
  42. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:220-227 [Conf]
  43. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems: application to timing optimization of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:324-331 [Conf]
  44. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Synthesizing Petri nets from state-based models. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:164-171 [Conf]
  45. Hiroshi Saito, Alex Kondratyev, Jordi Cortadella, Luciano Lavagno, Alexandre Yakovlev
    What is the cost of delay insensitivity? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:316-323 [Conf]
  46. Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    A unified signal transition graph model for asynchronous control circuit synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:104-111 [Conf]
  47. Yu Zhou, Danil Sokolov, Alexandre Yakovlev
    Cost-aware synthesis of asynchronous circuits based on partial acknowledgement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:158-163 [Conf]
  48. Alexandre Yakovlev
    On Limitations and Extensions of STG Model for Designing Asynchronous Control Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:396-400 [Conf]
  49. Fei Hao, Fei Xia, E. Graeme Chester, Alexandre Yakovlev, Ian G. Clark
    MATLAB Models of ACMS in Control Systems. [Citation Graph (0, 0)][DBLP]
    ICINCO (3), 2004, pp:54-61 [Conf]
  50. Alex Kondratyev, Leonid Ya. Rosenblum, Alexandre Yakovlev
    Signal Graphs: A Model for Designing Concurrent Logic. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1988, pp:51-54 [Conf]
  51. Leonid Ya. Rosenblum, Alexandre Yakovlev
    Analyzing Semantics of Concurrent Hardware Specifications. [Citation Graph (0, 0)][DBLP]
    ICPP (3), 1989, pp:211-218 [Conf]
  52. Alexandre Yakovlev, A. I. Petrov, Leonid Ya. Rosenblum
    Synthesis of Asynchronous Control Circuits from Symbolic Signal Transition Graphs. [Citation Graph (0, 0)][DBLP]
    Asynchronous Design Methodologies, 1993, pp:71-85 [Conf]
  53. Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev, Deepali Koppad
    On-Line Testing of Globally Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:135-140 [Conf]
  54. Julian Murphy, Alexandre V. Bystrov, Alexandre Yakovlev
    Power-Balanced Self Checking Circuits for Cryptographic Chips. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2005, pp:157-162 [Conf]
  55. Deepali Koppad, Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev
    Online Testing by Protocol Decomposition. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2006, pp:263-268 [Conf]
  56. Oleh V. Maevsky, D. J. Kinniment, Alexandre Yakovlev, Alexandre V. Bystrov
    Analysis of the oscillation problem in tri-flops. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:381-384 [Conf]
  57. Delong Shang, Fei Xia, Alexandre Yakovlev
    Asynchronous circuit synthesis via direct translation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:369-372 [Conf]
  58. Jun Zhou, David Kinniment, Gordon Russell, Alex Yakovlev
    A Robust Synchronizer. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:442-443 [Conf]
  59. Alexandre V. Bystrov, Alexandre Yakovlev
    Synthesis of Asynchronous Circuits with Predictable Latency. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:239-243 [Conf]
  60. Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev
    Visualization of Coding Conflicts in Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:155-160 [Conf]
  61. Crescenzo D'Alessandro, Delong Shang, Alexandre V. Bystrov, Alexandre Yakovlev
    PSK Signalling on NoC Buses. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:286-296 [Conf]
  62. D. J. Kinniment, Alexandre Yakovlev
    Low Latency Synchronization Through Speculation. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:278-288 [Conf]
  63. Delong Shang, Frank P. Burns, Alexandre V. Bystrov, Alexandre V. Koelmans, Danil Sokolov, Alexandre Yakovlev
    A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:471-480 [Conf]
  64. Nikolai Starodoubtsev, Alexandre V. Bystrov, Alexandre Yakovlev
    Semi-modular Latch Chains for Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:168-177 [Conf]
  65. Leonid Ya. Rosenblum, Alexandre Yakovlev
    Signal Graphs: From Self-Timed to Timed Ones. [Citation Graph (0, 0)][DBLP]
    PNPM, 1985, pp:199-206 [Conf]
  66. Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside
    Logic Design of Asynchronous Circuits (Tutorial Abstract). [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:26-0 [Conf]
  67. Deepali Koppad, Alexandre V. Bystrov, Alexandre Yakovlev
    Off-Line Testing of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:730-735 [Conf]
  68. Alexandre Yakovlev
    Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:21-24 [Conf]
  69. Alan Burns, Andy J. Wellings, Frank P. Burns, Albert Koelmans, Maciej Koutny, Alexander B. Romanovsky, Alexandre Yakovlev
    Modelling and verification of an atomic action protocol implemented in Ada. [Citation Graph (0, 0)][DBLP]
    Comput. Syst. Sci. Eng., 2001, v:16, n:3, pp:173-182 [Journal]
  70. Alexandre Yakovlev, Albert Koelmans, Luciano Lavagno
    High-Level Modeling and Design of Asynchronous Interface Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:1, pp:32-40 [Journal]
  71. Leonid Ya. Rosenblum, Alexandre Yakovlev, Vladimir Yakovlev
    A look at concurrency semantics through "lattice glasses". [Citation Graph (0, 0)][DBLP]
    Bulletin of the EATCS, 1989, v:37, n:, pp:175-180 [Journal]
  72. Sohini Dasgupta, Dumitru Potop-Butucaru, Benoît Caillaud, Alex Yakovlev
    Moving from Weakly Endochronous Systems to Delay-Insensitive Circuits. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:81-103 [Journal]
  73. Alexandre Yakovlev
    Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1998, v:12, n:1, pp:39-71 [Journal]
  74. Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny
    On the Models for Asynchronous Circuit Behaviour with OR Causality. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1996, v:9, n:3, pp:189-233 [Journal]
  75. Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1996, v:9, n:3, pp:139-188 [Journal]
  76. Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
    Detecting State Encoding Conflicts in STG Unfoldings Using SAT. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2004, v:62, n:2, pp:221-241 [Journal]
  77. Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
    Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2006, v:70, n:1-2, pp:49-73 [Journal]
  78. Fei Xia, Fei Hao, Ian G. Clark, Alexandre Yakovlev, E. Graeme Chester
    Buffered Asynchronous Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2006, v:70, n:1-2, pp:155-170 [Journal]
  79. Alexandre Yakovlev, Albert Koelmans, Alexei L. Semenov, D. J. Kinniment
    Modelling, analysis and synthesis of asynchronous control circuits using Petri nets. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:3, pp:143-170 [Journal]
  80. Fei Xia, Alexandre Yakovlev, Ian G. Clark, Delong Shang
    Data Communication in Systems with Heterogeneous Timing. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:6, pp:58-69 [Journal]
  81. Frank P. Burns, Albert Koelmans, Alexandre Yakovlev
    WCET Analysis of Superscalar Processors Using Simulation With Coloured Petri Nets. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2000, v:18, n:2/3, pp:275-288 [Journal]
  82. Frank P. Burns, Albert Koelmans, Alexandre Yakovlev
    Analysing Superscalar Processor Architectures with Coloured Petri Nets. [Citation Graph (0, 0)][DBLP]
    STTT, 1998, v:2, n:2, pp:182-191 [Journal]
  83. Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexandre Yakovlev
    Deriving Petri Nets for Finite Transition Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:8, pp:859-882 [Journal]
  84. Danil Sokolov, Julian Murphy, Alexandre V. Bystrov, Alexandre Yakovlev
    Design and Analysis of Dual-Rail Circuits for Security Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:4, pp:449-460 [Journal]
  85. Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov
    Design and Analysis of a Self-Timed Duplex Communication System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:7, pp:798-814 [Journal]
  86. Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev
    Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:109-130 [Journal]
  87. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1221-1236 [Journal]
  88. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexandre Yakovlev
    A region-based theory for state assignment in speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:8, pp:793-812 [Journal]
  89. Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev
    Hazard-free implementation of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:749-771 [Journal]
  90. D. J. Kinniment, Oleh V. Maevsky, Alexandre V. Bystrov, Gordon Russell, Alexandre Yakovlev
    On-chip structures for timing measurement and test. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:9, pp:473-483 [Journal]
  91. Yuan Chen, Fei Xia, Delong Shang, Alexandre Yakovlev
    The Design of Virtual Self-timed Block for Activity Communication in SOC. [Citation Graph (0, 0)][DBLP]
    ACSD, 2007, pp:100-109 [Conf]
  92. Danil Sokolov, Ivan Poliakov, Alex Yakovlev
    Asynchronous Data Path Models. [Citation Graph (0, 0)][DBLP]
    ACSD, 2007, pp:197-210 [Conf]
  93. K. T. Gardiner, Alexandre Yakovlev, Alexandre V. Bystrov
    A C-element Latch Scheme with Increased Transient Fault Tolerance for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:223-230 [Conf]
  94. Yuan Chen, Fei Xia, Alexandre Yakovlev
    Virtual self-timed blocks for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  95. Delong Shang, Chi-Hoon Shin, Ping Wang, Fei Xia, Albert Koelmans, Myeong-Hoon Oh, Seongwoon Kim, Alexandre Yakovlev
    Asynchronous Functional Coupling for Low Power Sensor Network Processors. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2007, pp:53-63 [Conf]
  96. Delong Shang, Alexandre Yakovlev, Frank P. Burns, Fei Xia, Alexandre V. Bystrov
    Low-Cost Online Testing of Asynchronous Handshakes. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:225-232 [Conf]
  97. Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini
    Reducing Interconnect Cost in NoC through Serialized Asynchronous Links. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:219- [Conf]
  98. Crescenzo D'Alessandro, Nikolaos Minas, Keith Heron, David Kinniment, Alexandre Yakovlev
    NoC Communication Strategies Using Time-to-Digital Conversion. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:65-74 [Conf]
  99. Kyller Costa Gorgônio, Jordi Cortadella, Fei Xia, Alexandre Yakovlev
    Automating Synthesis of Asynchronous Communication Mechanisms. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2007, v:78, n:1, pp:75-100 [Journal]
  100. Delong Shang, Alexandre Yakovlev, Albert Koelmans, Danil Sokolov, Alexandre V. Bystrov
    Registers for Phase Difference Based Logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:6, pp:720-724 [Journal]
  101. David Kinniment, Charles E. Dike, Keith Heron, Gordon Russell, Alexandre Yakovlev
    Measuring Deep Metastability and Its Effect on Synchronizer Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:1028-1039 [Journal]
  102. David Kinniment, Alexandre Yakovlev, B. Gao
    Synchronous and asynchronous A-D conversion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:217-220 [Journal]

  103. Verification of conditional partial order graphs. [Citation Graph (, )][DBLP]


  104. Flat Arbiters. [Citation Graph (, )][DBLP]


  105. Synthesis of Nets with Step Firing Policies. [Citation Graph (, )][DBLP]


  106. Workcraft - A Framework for Interpreted Graph Models. [Citation Graph (, )][DBLP]


  107. A Symbolic Algorithm for the Synthesis of Bounded Petri Nets. [Citation Graph (, )][DBLP]


  108. Asynchronous transient resilient links for NoC. [Citation Graph (, )][DBLP]


  109. Conditional Partial Order Graphs and Dynamically Reconfigurable Control Synthesis. [Citation Graph (, )][DBLP]


  110. Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods. [Citation Graph (, )][DBLP]


  111. Serialized Asynchronous Links for NoC. [Citation Graph (, )][DBLP]


  112. Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis. [Citation Graph (, )][DBLP]


  113. Conversion driven design of binary to mixed radix circuits. [Citation Graph (, )][DBLP]


  114. Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits. [Citation Graph (, )][DBLP]


  115. Secure Design Flow for Asynchronous Multi-valued Logic Circuits. [Citation Graph (, )][DBLP]


  116. The Magic Rule of Tiles: Virtual Delay Insensitivity. [Citation Graph (, )][DBLP]


  117. The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk. [Citation Graph (, )][DBLP]


  118. Global interconnections in FPGAs: modeling and performance analysis. [Citation Graph (, )][DBLP]


  119. Implementation of Wave-Pipelined Interconnects in FPGAs. [Citation Graph (, )][DBLP]


  120. Connection-centric network for spiking neural networks. [Citation Graph (, )][DBLP]


  121. Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. [Citation Graph (, )][DBLP]


  122. Desynchronisation Technique Using Petri Nets. [Citation Graph (, )][DBLP]


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