The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Enric Pastor: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Josep Carmona, Jordi Cortadella, Enric Pastor
    Synthesis of Reactive Systems: Application to Asynchronous Circuit Design. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:108-151 [Conf]
  2. Josep Carmona, Jordi Cortadella, Enric Pastor
    A structural encoding technique for the synthesis of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    ACSD, 2001, pp:157-166 [Conf]
  3. Marc Solé, Enric Pastor
    Evaluating Symbolic Traversal Algorithms Applied to Asynchronous Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    ACSD, 2004, pp:207-216 [Conf]
  4. Oriol Roig, Jordi Cortadella, Enric Pastor
    Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets. [Citation Graph (0, 0)][DBLP]
    Application and Theory of Petri Nets, 1995, pp:374-391 [Conf]
  5. Enric Pastor, Jordi Cortadella, Marco A. Peña
    Structural Methods to Improve the Symbolic Analysis of Petri Nets. [Citation Graph (0, 0)][DBLP]
    ICATPN, 1999, pp:26-45 [Conf]
  6. Enric Pastor, Oriol Roig, Jordi Cortadella, Rosa M. Badia
    Petri Net Analysis Using Boolean Manipulation. [Citation Graph (0, 0)][DBLP]
    Application and Theory of Petri Nets, 1994, pp:416-435 [Conf]
  7. Marco A. Peña, Jordi Cortadella, Enric Pastor, Alex Kondratyev
    Formal Verification of Safety Properties in Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:2-11 [Conf]
  8. Oriol Roig, Jordi Cortadella, Enric Pastor
    Hierarchical gate-level verification of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1995, pp:128-137 [Conf]
  9. Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella, Luciano Lavagno
    Partial order based approach to synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 1997, pp:254-0 [Conf]
  10. Enric Pastor, Marco A. Peña, Marc Solé
    TRANSYT: A Tool for the Verification of Asynchronous Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 2005, pp:424-428 [Conf]
  11. Enric Pastor, Marco A. Peña
    Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:378-393 [Conf]
  12. Oriol Roig, Jordi Cortadella, Marco A. Peña, Enric Pastor
    Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:620-625 [Conf]
  13. Alexei L. Semenov, Alexandre Yakovlev, Enric Pastor, Marco A. Peña, Jordi Cortadella
    Synthesis of Speed-Independent Circuits from STG-Unfolding Segment. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:16-21 [Conf]
  14. Enric Pastor, Jordi Cortadella
    Efficient Encoding Schemes for Symbolic Analysis of Petri Nets. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:790-795 [Conf]
  15. Enric Pastor, Marco A. Peña
    Combining Simulation and Guided Traversal for the Verification of Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11158-11159 [Conf]
  16. Marco A. Peña, Jordi Cortadella, Alexander B. Smirnov, Enric Pastor
    A Case Study for the Verification of Complex Timed Circuits: IPCMOS. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:44-53 [Conf]
  17. Marc Solé, Enric Pastor
    Traversal Techniques for Concurrent Systems. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2002, pp:220-237 [Conf]
  18. Enric Pastor, Jordi Cortadella, Oriol Roig
    A new look at the conditions for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:230-0 [Conf]
  19. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:220-227 [Conf]
  20. Enric Pastor, Jordi Cortadella
    Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:250-254 [Conf]
  21. Enric Pastor, Jordi Cortadella
    An Efficient Unique State Coding Algorithm for Signal Transition Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:174-177 [Conf]
  22. Josep Carmona, Jordi Cortadella, Enric Pastor
    A structural encoding technique for the synthesis of asynchronous circuits. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2002, v:50, n:2, pp:135-154 [Journal]
  23. Enric Pastor, Jordi Cortadella, Oriol Roig
    Symbolic Analysis of Bounded Petri Nets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:5, pp:432-448 [Journal]
  24. Jordi Cortadella, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Enric Pastor, Alexandre Yakovlev
    Decomposition and technology mapping of speed-independent circuits using Boolean relations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1221-1236 [Journal]
  25. Enric Pastor, Jordi Cortadella, Alex Kondratyev, Oriol Roig
    Structural methods for the synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:11, pp:1108-1129 [Journal]

  26. A middleware architecture for unmanned aircraft avionics. [Citation Graph (, )][DBLP]


  27. BMC Encoding for Concurrent Systems. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.305secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002