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Felice Balarin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe
    Modeling and Designing Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:228-273 [Conf]
  2. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Case Studies of Model Checking for Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:20-28 [Conf]
  3. Felice Balarin
    Correctness of the Concurrent Approach to Symbolic Verification of Interleaved Models. [Citation Graph (0, 0)][DBLP]
    CAV, 1998, pp:391-402 [Conf]
  4. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    A Verification Strategy for Timing-Constrained Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1992, pp:151-163 [Conf]
  5. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    An Iterative Approach to Language Containment. [Citation Graph (0, 0)][DBLP]
    CAV, 1993, pp:29-40 [Conf]
  6. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    On the Automatic Computation of Network Invariants. [Citation Graph (0, 0)][DBLP]
    CAV, 1994, pp:234-246 [Conf]
  7. Adnan Aziz, Felice Balarin, Robert K. Brayton, M. D. DiBenedetto, Alexander Saldanha
    Supervisory Control of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:279-292 [Conf]
  8. Adnan Aziz, Vigyan Singhal, Felice Balarin
    It Usually Works: The Temporal Logic of Stochastic Systems. [Citation Graph (0, 0)][DBLP]
    CAV, 1995, pp:155-165 [Conf]
  9. Felice Balarin, Gary York
    Verilog HDL Modeling Styles for Formal Verification. [Citation Graph (0, 0)][DBLP]
    CHDL, 1993, pp:453-465 [Conf]
  10. Felice Balarin
    STARS of MPEG decoder: a case study in worst-case analysis of discrete-event systems. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:104-108 [Conf]
  11. Felice Balarin
    Worst-case analysis of discrete systems based on conditional abstractions. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:115-119 [Conf]
  12. Felice Balarin, Massimiliano Chiodo, Attila Jurecska, Luciano Lavagno, Bassam Tabbara, Alberto L. Sangiovanni-Vincentelli
    Automatic Generation of a Real-Time Operating System for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1997, pp:95-100 [Conf]
  13. Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang
    Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:13-18 [Conf]
  14. Adnan Aziz, Felice Balarin, Szu-Tsung Cheng, Ramin Hojati, Timothy Kam, Sriram C. Krishnan, Rajeev K. Ranjan, Thomas R. Shiple, Vigyan Singhal, Serdar Tasiran, Huey-Yih Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    HSIS: A BDD-Based Environment for Formal Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:454-459 [Conf]
  15. Felice Balarin, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Formal Verification of Embedded Systems based on CFSM Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:568-571 [Conf]
  16. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    Schedule Validation for Embedded Reactive Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:52-57 [Conf]
  17. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Automatic trace analysis for logic of constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:460-465 [Conf]
  18. Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Efficient methods for embedded system design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:607-612 [Conf]
  19. Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin
    Task scheduling with RT constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:483-488 [Conf]
  20. Felice Balarin
    Automatic Abstraction for Worst-Case Analysis of Discrete Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:494-501 [Conf]
  21. Felice Balarin, Roberto Passerone
    Functional verification methodology based on formal interface specification and transactor generation. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1013-1018 [Conf]
  22. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11174-11175 [Conf]
  23. Xi Chen, Yan Luo, Harry Hsieh, Laxmi N. Bhuyan, Felice Balarin
    Utilizing Formal Assertions for System Design of Network Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:126-133 [Conf]
  24. Guang Yang, Xi Chen, Felice Balarin, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli
    Communication and co-simulation infrastructure for heterogeneous system integration. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:462-467 [Conf]
  25. Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
    Assertion-Based Design Exploration of DVS in Network Processor Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:92-97 [Conf]
  26. Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
    Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2002, pp:407-416 [Conf]
  27. Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin
    Separation of concerns: overhead in modeling and efficient simulation techniques. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:44-53 [Conf]
  28. Adnan Aziz, Vigyan Singhal, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Equivalences for Fair Kripke Structures. [Citation Graph (0, 0)][DBLP]
    ICALP, 1994, pp:364-375 [Conf]
  29. Felice Balarin
    Stars in VCC: Complementing Simulation with Worst-Case Analysis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:471-0 [Conf]
  30. Felice Balarin
    Worst-case analysis of discrete systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:347-353 [Conf]
  31. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    Iterative algorithms for formal verification of embedded real-time systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:450-457 [Conf]
  32. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:612-617 [Conf]
  33. Harry Hsieh, Felice Balarin
    Synchronous equivalence for embedded systems: a tool for design exploration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:505-510 [Conf]
  34. Felice Balarin, Massimiliano Chiodo
    Software Synthesis for Complex Reactive Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:634-639 [Conf]
  35. Felice Balarin
    Priority Assignment for Embedded Reactive Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 1998, pp:146-155 [Conf]
  36. Felice Balarin, Claudio Passerone, Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli
    A formal approach to system level design: metamodels and unified design environments. [Citation Graph (0, 0)][DBLP]
    MEMOCODE, 2005, pp:155-163 [Conf]
  37. Marco Di Natale, Alberto L. Sangiovanni-Vincentelli, Felice Balarin
    Scheduling Reactive Task Graphs in Embedded Control Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2001, pp:191-0 [Conf]
  38. Felice Balarin
    Approximate reachability analysis of timed automata. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1996, pp:52-61 [Conf]
  39. Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli
    Metropolis: An Integrated Electronic System Design Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:45-52 [Journal]
  40. Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli
    Scheduling for Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:71-82 [Journal]
  41. Felice Balarin
    Verifying invariants by approximate image computation. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 1997, v:9, n:, pp:- [Journal]
  42. Felice Balarin
    Concurrent Symbolic Verification of Liveness Properties for Interleaved Models. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 1999, v:23, n:2, pp:- [Journal]
  43. Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    An Iterative Approach to Verification of Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1995, v:6, n:1, pp:67-95 [Journal]
  44. Xi Chen, Harry Hsieh, Felice Balarin
    Verification Approach of Metropolis Design Framework for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2006, v:34, n:1, pp:3-27 [Journal]
  45. Adnan Aziz, Felice Balarin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Sequential synthesis using S1S. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:10, pp:1149-1162 [Journal]
  46. Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli, Ellen Sentovich, Kei Suzuki
    Synthesis of software programs for embedded control applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:834-849 [Journal]
  47. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Logic of constraints: a quantitative performance and functional constraint formalism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1243-1255 [Journal]
  48. Harry Hsieh, Felice Balarin, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Synchronous approach to the functional equivalence of embeddedsystem implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:8, pp:1016-1033 [Journal]
  49. Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin
    Assertion-Based Design Exploration of DVS in Network Processor Architectures [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  50. Partial order method for timed simulation of system-level MPSoC designs. [Citation Graph (, )][DBLP]


  51. Memory subsystem simulation in software TLM/T models. [Citation Graph (, )][DBLP]


  52. Fast and accurate performance simulation of embedded software for MPSoC. [Citation Graph (, )][DBLP]


  53. Software optimization for MPSoC: a mpeg-2 decoder case study. [Citation Graph (, )][DBLP]


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