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Yosinori Watanabe: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe
    Modeling and Designing Heterogeneous Systems. [Citation Graph (0, 0)][DBLP]
    Concurrency and Hardware Design, 2002, pp:228-273 [Conf]
  2. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Case Studies of Model Checking for Embedded System Designs. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:20-28 [Conf]
  3. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe
    Quasi-Static Scheduling for Concurrent Architectures. [Citation Graph (0, 0)][DBLP]
    ACSD, 2003, pp:29-40 [Conf]
  4. Shinjiro Kakita, Yosinori Watanabe, Douglas Densmore, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli
    Functional Model Exploration for Multimedia Applications via Algebraic Operators. [Citation Graph (0, 0)][DBLP]
    ACSD, 2006, pp:229-238 [Conf]
  5. Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli, Jorg Desel
    Schedulability Analysis of Petri Nets Based on Structural Properties. [Citation Graph (0, 0)][DBLP]
    ACSD, 2006, pp:69-78 [Conf]
  6. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
    Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. [Citation Graph (0, 0)][DBLP]
    ICATPN, 2002, pp:80-100 [Conf]
  7. Marco Sgroi, Luciano Lavagno, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
    Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets. [Citation Graph (0, 0)][DBLP]
    ICATPN, 1999, pp:208-227 [Conf]
  8. Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang
    Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:13-18 [Conf]
  9. H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
    Designing digital video systems: modeling and scheduling. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:64-68 [Conf]
  10. Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Temporofunctional crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:860-863 [Conf]
  11. Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
    Simulation based deadlock analysis for system level designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:260-265 [Conf]
  12. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Automatic trace analysis for logic of constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:460-465 [Conf]
  13. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
    Task generation and compile-time scheduling for mixed data-control embedded software. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:489-494 [Conf]
  14. Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska
    Gain-based technology mapping for discrete-size cell libraries. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:574-579 [Conf]
  15. Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten
    Area and search space control for technology mapping. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:86-91 [Conf]
  16. G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe
    False Path Elimination in Quasi-Static Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:964-970 [Conf]
  17. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11174-11175 [Conf]
  18. Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe
    A Time Slice Based Scheduler Model for System Level Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:378-383 [Conf]
  19. Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev
    An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10428-10435 [Conf]
  20. Claudio Passerone, Yosinori Watanabe, Luciano Lavagno
    Generation of minimal size code for scheduling graphs. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:668-673 [Conf]
  21. Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating False Positives in Crosstalk Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1192-1197 [Conf]
  22. Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
    Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2002, pp:407-416 [Conf]
  23. Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
    A structural approach to quasi-static schedulability analysis of communicating concurrent programs. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2005, pp:10-16 [Conf]
  24. Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin
    Separation of concerns: overhead in modeling and efficient simulation techniques. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:44-53 [Conf]
  25. Yosinori Watanabe, Robert K. Brayton
    State Minimization of Pseudo Non-Deterministic FSM's. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:184-191 [Conf]
  26. Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
    Logic decomposition during technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:264-271 [Conf]
  27. Yosinori Watanabe, Robert K. Brayton
    The maximum set of permissible behaviors for FSM networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:316-320 [Conf]
  28. Yosinori Watanabe, Robert K. Brayton
    Heuristic Minimazation of Multiple-Valued Relations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:126-129 [Conf]
  29. Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton
    Heuristic Minimization of Synchronous Relations. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:428-433 [Conf]
  30. Yosinori Watanabe, Robert K. Brayton
    Incremental Synthesis for Engineering Changes. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:40-43 [Conf]
  31. Yosinori Watanabe, Lisa Guerra, Robert K. Brayton
    Logic Optimization with Multi-Output Gates. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:416-420 [Conf]
  32. Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli
    Metropolis: An Integrated Electronic System Design Environment. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:45-52 [Journal]
  33. Gianpiero Cabodi, Sergio Nocco, Stefano Quer, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe
    A BMC-formulation for the scheduling problem in highly constrained hardware Systems. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2003, v:89, n:4, pp:- [Journal]
  34. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Yosinori Watanabe
    Quasi-static Scheduling for Concurrent Architectures. [Citation Graph (0, 0)][DBLP]
    Fundam. Inform., 2004, v:62, n:2, pp:171-196 [Journal]
  35. Gianpiero Cabodi, Alex Kondratyev, Luciano Lavagno, Sergio Nocco, Stefano Quer, Yosinori Watanabe
    A BMC-based formulation for the scheduling problem of hardware systems. [Citation Graph (0, 0)][DBLP]
    STTT, 2005, v:7, n:2, pp:102-117 [Journal]
  36. Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
    Logic of constraints: a quantitative performance and functional constraint formalism. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:8, pp:1243-1255 [Journal]
  37. Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
    Quasi-static scheduling of independent tasks for reactive systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1492-1514 [Journal]
  38. Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating false positives in crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1406-1419 [Journal]
  39. Yosinori Watanabe, Robert K. Brayton
    Heuristic minimization of multiple-valued relations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1458-1472 [Journal]
  40. Yosinori Watanabe, Lisa Guerra, Robert K. Brayton
    Permissible functions for multioutput components in combinational logic optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:732-744 [Journal]

  41. Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs. [Citation Graph (, )][DBLP]


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