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Title:
Author:
Wolfgang Fichtner: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Wolfgang Fichtner
    Design of VLSI Systems. [Citation Graph (0, 0)][DBLP]
    Embedded Systems, 1986, pp:6-17 [Conf]
  2. Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner
    Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2003, pp:141-150 [Conf]
  3. Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:181-189 [Conf]
  4. Jens Muttersbach, Thomas Villiger, Wolfgang Fichtner
    Practical Design of Globally-Asynchronous Locally-Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:52-0 [Conf]
  5. Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    GALS at ETH Zurich: Success or Failure. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2006, pp:150-159 [Conf]
  6. A. K. Lutz, J. Treichler, Frank K. Gürkaynak, Hubert Kaeslin, G. Basler, Antonia Erni, S. Reichmuth, P. Rommens, Stephan Oetiker, Wolfgang Fichtner
    2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. [Citation Graph (0, 0)][DBLP]
    CHES, 2002, pp:144-158 [Conf]
  7. Felix Bürgin, Flavio Carbognani, Martin Hediger, Hektor Meier, Robert Meyer-Piening, Rafael Santschi, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    Low-power architectural trade-offs in a VLSI implementation of an adaptive hearing aid algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:558-561 [Conf]
  8. Alexander Herrigel, Wolfgang Fichtner
    An Analytic Optimization Technique for Placement of Macro-Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:376-381 [Conf]
  9. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    Two-phase resonant clocking for ultra-low-power hearing aid applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:73-78 [Conf]
  10. Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin
    A 2 Gb/s balanced AES crypto-chip implementation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:39-44 [Conf]
  11. C. Hess, M. Wenk, Andreas Burg, P. Luethi, Christoph Studer, Norbert Felber, Wolfgang Fichtner
    Reduced-complexity mimo detector with close-to ml error rate performance. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:200-203 [Conf]
  12. Olaf Schenk, Klaus Gärtner, Wolfgang Fichtner
    Scalable Parallel Sparse Factorization with Left-Right Looking Strategy on Shared Memory Multoprocessors. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1999, pp:221-230 [Conf]
  13. Steven J. Seda, Marc G. R. Degrauwe, Wolfgang Fichtner
    Lazy-expansion symbolic expression approximation in SYNAP. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:310-317 [Conf]
  14. Nancy Hitschfeld, Stephan Müller, Wolfgang Fichtner
    Generation of 3-D Delaunay Meshes for Complex Geometries using Iterative Refinement. [Citation Graph (0, 0)][DBLP]
    IFIP Congress (1), 1992, pp:388-394 [Conf]
  15. Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner
    Variable delay ripple carry adder with carry chain interrupt detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:113-116 [Conf]
  16. J. Thalheim, Norbert Felber, Wolfgang Fichtner
    A new approach for controlling series-connected IGBT modules. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:69-72 [Conf]
  17. Olaf Schenk, Klaus Gärtner, Wolfgang Fichtner
    Application of Parallel Sparse Direct Methods in Semiconductor Device and Process Simulation. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1999, pp:206-219 [Conf]
  18. H. Bonnenberg, Andreas Curiger, Norbert Felber, Hubert Kaeslin, R. Zimmermann, Wolfgang Fichtner
    VINCI: Secure Test of a VLSI High-Speed Encryption System. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:782-790 [Conf]
  19. Manfred Stadler, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner, Markus Thalmann
    Functional verification of intellectual properties (IP): a simulation-based solution for an application-specific instruction-set processor. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:414-420 [Conf]
  20. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    Two-Phase Clocking and a New Latch Design for Low-Power Portable Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:446-455 [Conf]
  21. Arno Liegmann, Wolfgang Fichtner
    Solving Large Sparse Linear Systems in a Distributed Computing Environment. [Citation Graph (0, 0)][DBLP]
    PPSC, 1995, pp:496-497 [Conf]
  22. Claude Pommerell, Wolfgang Fichtner
    PILS: an iterative linear solver package for ill-conditioned systems. [Citation Graph (0, 0)][DBLP]
    SC, 1991, pp:588-599 [Conf]
  23. Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:146, n:2, pp:133-149 [Journal]
  24. Olaf Schenk, Klaus Gärtner, Wolfgang Fichtner, Andreas Stricker
    PARDISO: a high-performance serial and parallel sparse linear solver in semiconductor device simulation. [Citation Graph (0, 0)][DBLP]
    Future Generation Comp. Syst., 2001, v:18, n:1, pp:69-78 [Journal]
  25. Clemens Czernohous, Wolfgang Fichtner, Daniel Veit, Christof Weinhardt
    Management decision support using long-term market simulation. [Citation Graph (0, 0)][DBLP]
    Inf. Syst. E-Business Management, 2003, v:1, n:4, pp:405-423 [Journal]
  26. Manfred Stadler, Markus Thalmann, Thomas Röwer, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner
    Design and Verification of a Stack Processor Virtual Component. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2001, v:21, n:2, pp:69-80 [Journal]
  27. Randolph E. Bank, William M. Coughran Jr., Wolfgang Fichtner, Eric Grosse, Donald J. Rose, R. Kent Smith
    Transient Simulation of Silicon Devices and Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:4, pp:436-451 [Journal]
  28. Josef F. Burgler, Randolph E. Bank, Wolfgang Fichtner, R. Kent Smith
    A new discretization scheme for the semiconductor current continuity equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:5, pp:479-489 [Journal]
  29. Josef F. Burgler, William M. Coughran Jr., Wolfgang Fichtner
    An adaptive grid refinement strategy for the drift-diffusion equations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:10, pp:1251-1258 [Journal]
  30. Paolo Conti, Nancy Hitschfeld-Kahler, Wolfgang Fichtner
    Omega-an octree-based mixed element grid allocator for the simulation of complex 3-D device structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:10, pp:1231-1241 [Journal]
  31. William M. Coughran Jr., Wolfgang Fichtner, Eric Grosse
    Extracting transistor changes from device simulations by gradient fitting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:4, pp:380-394 [Journal]
  32. Hans-Rudolf Heeb, Wolfgang Fichtner
    A module generator based on the PQ-tree algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:876-884 [Journal]
  33. Gernot Heiser, Claude Pommerell, Jürgen Weis, Wolfgang Fichtner
    Three-dimensional numerical semiconductor device simulation: algorithms, architectures, results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:10, pp:1218-1230 [Journal]
  34. Nancy Hitschfeld-Kahler, Paolo Conti, Wolfgang Fichtner
    Mixed element trees: a generalization of modified octrees for the generation of meshes for the simulation of complex 3-D semiconductor device structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:11, pp:1714-1725 [Journal]
  35. Stephan Müller, Kevin Kells, Wolfgang Fichtner
    Automatic rectangle-based adaptive mesh generation without obtuse angles. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:7, pp:855-863 [Journal]
  36. G. W. Taylor, Wolfgang Fichtner, J. G. Simmons
    A Description of MOS Internodal Capacitances for Transient Simulations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1982, v:1, n:4, pp:150-156 [Journal]
  37. P. Douglas Yoder, Klaus Gärtner, Ulrich Krumbein, Wolfgang Fichtner
    Optimized terminal current calculation for Monte Carlo device simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:10, pp:1082-1087 [Journal]
  38. H. Yabuhara, Mauro Ciappa, Wolfgang Fichtner
    Diamond-Coated Cantilevers for Scanning Capacitance Microscopy Applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:9-10, pp:1459-1463 [Journal]
  39. Michael Schenkel, Paul Pfäffli, Wolfgang Wilkening, D. Aemmer, Wolfgang Fichtner
    Substrate potential shift due to parasitic minority carrier injection in smart-power ICs: measurements and full-chip 3D device simulation. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:6, pp:815-822 [Journal]
  40. K. Esmark, Wolfgang Stadler, M. Wendel, Harald Gossner, X. Guggenmos, Wolfgang Fichtner
    Advanced 2D/3D ESD device simulation - a powerful tool already used in a pre-Si phase. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:11, pp:1761-1770 [Journal]
  41. Mauro Ciappa, Flavio Carbognani, P. Cova, Wolfgang Fichtner
    A Novel Thermomechanics -Based Lifetime Prediction Model for Cycle Fatigue Failure Mechanisms in Power Semiconductors. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:9-11, pp:1653-1658 [Journal]
  42. Wolfgang Stadler, K. Esmark, Harald Gossner, M. Streibl, M. Wendel, Wolfgang Fichtner, Dionyz Pogany, Martin Litzenberger, E. Gornik
    Device Simulation and Backside Laser Interferometry--Powerful Tools for ESD Protection Development. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:9-11, pp:1267-1274 [Journal]
  43. Maria Stangoni, Mauro Ciappa, Marco Buzzo, M. Leicht, Wolfgang Fichtner
    Simulation and Experimental Validation of Scanning Capacitance Microscopy Measurements across Low-doped Epitaxial PN-Junction. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:9-11, pp:1701-1706 [Journal]
  44. Maria Stangoni, Mauro Ciappa, Wolfgang Fichtner
    A New Procedure to Define the Zero-Field Condition and to Delineate pn-Junctions in Silicon Devices by Scanning Capacitance Microscopy. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1651-1656 [Journal]
  45. G. Mura, Massimo Vanzi, Maria Stangoni, Mauro Ciappa, Wolfgang Fichtner
    On the behaviour of the selective iodine-based gold etch for the failure analysis of aged optoelectronic devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:9-11, pp:1771-1776 [Journal]
  46. Marco Buzzo, Mauro Ciappa, Maria Stangoni, Wolfgang Fichtner
    Two-dimensional Dopant Profiling and Imaging of 4H Silicon Carbide Devices by Secondary Electron Potential Contrast. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:9-11, pp:1499-1504 [Journal]
  47. Maria Stangoni, Mauro Ciappa, Wolfgang Fichtner
    Assessment of the Analytical Capabilities of Scanning Capacitance and Scanning Spreading Resistance Microscopy Applied to Semiconductor Devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:9-11, pp:1532-1537 [Journal]
  48. Mauro Ciappa, Wolfgang Fichtner, T. Kojima, Y. Yamada, Y. Nishibe
    Extraction of Accurate Thermal Compact Models for Fast Electro-Thermal Simulation of IGBT Modules in Hybrid Electric Vehicles. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:9-11, pp:1694-1699 [Journal]
  49. Marco Buzzo, Mauro Ciappa, Wolfgang Fichtner
    Characterization of photonic devices by secondary electron potential contrast. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:9-11, pp:1536-1541 [Journal]
  50. Alberto Castellazzi, Mauro Ciappa, Wolfgang Fichtner, G. Lourdel, Michel Mermet-Guyennet
    Compact modelling and analysis of power-sharing unbalances in IGBT-modules used in traction applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:9-11, pp:1754-1759 [Journal]
  51. D. Barlini, Mauro Ciappa, Alberto Castellazzi, Michel Mermet-Guyennet, Wolfgang Fichtner
    New technique for the measurement of the static and of the transient junction temperature in IGBT devices under operating conditions. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2006, v:46, n:9-11, pp:1772-1777 [Journal]
  52. F. M. Bufler, A. Schenk, Wolfgang Fichtner
    Proof of a simple time-step propagation scheme for Monte Carlo simulation. [Citation Graph (0, 0)][DBLP]
    Mathematics and Computers in Simulation, 2003, v:62, n:3-6, pp:323-326 [Journal]
  53. Andreas Burg, S. Haene, Wolfgang Fichtner, M. Rupp
    Regularized Frequency Domain Equalization Algorithm and its VLSI Implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3530-3533 [Conf]
  54. Marc Simon Wegmueller, Martin Hediger, Thomas Kaufmann, Felix Bürgin, Wolfgang Fichtner
    Wireless Implant Communications for Biomedical Monitoring Sensor Network. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:809-812 [Conf]
  55. S. Haene, Andreas Burg, P. Luethi, Norbert Felber, Wolfgang Fichtner
    FFT Processor for OFDM Channel Estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1417-1420 [Conf]
  56. David Perels, Christoph Studer, Wolfgang Fichtner
    Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1903-1906 [Conf]
  57. P. Luethi, Andreas Burg, S. Haene, David Perels, Norbert Felber, Wolfgang Fichtner
    VLSI Implementation of a High-Speed Iterative Sorted MMSE QR Decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1421-1424 [Conf]
  58. M. Wenk, M. Zellweger, Andreas Burg, Norbert Felber, Wolfgang Fichtner
    K-best MIMO detection VLSI architectures achieving up to 424 Mbps. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  59. Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner
    42% power savings through glitch-reducing clocking strategy in a hearing aid application. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  60. S. Haene, Andreas Burg, David Perels, P. Luethi, Norbert Felber, Wolfgang Fichtner
    Silicon implementation of an MMSE-based soft demapper for MIMO-BICM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  61. Andreas Burg, S. Haene, David Perels, P. Luethi, Norbert Felber, Wolfgang Fichtner
    Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  62. S. C. Brugger, A. Schenk, Wolfgang Fichtner
    Moments of the Inverse Scattering Operator of the Boltzmann Equation: Theory and Applications. [Citation Graph (0, 0)][DBLP]
    SIAM Journal of Applied Mathematics, 2006, v:66, n:4, pp:1209-1226 [Journal]

  63. Hardware evaluation of the stream cipher-based hash functions RadioGatún and irRUPT. [Citation Graph (, )][DBLP]


  64. A Parallel Sparse Linear Solver for Nearest-Neighbor Tight-Binding Problems. [Citation Graph (, )][DBLP]


  65. Hardware-efficient steering matrix computation architecture for MIMO communication systems. [Citation Graph (, )][DBLP]


  66. VLSI architecture for data-reduced steering matrix feedback in MIMO systems. [Citation Graph (, )][DBLP]


  67. Multi-user MIMO testbed. [Citation Graph (, )][DBLP]


  68. Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications. [Citation Graph (, )][DBLP]


  69. Novel Solution for the Built-in Gate Oxide Stress Test of LDMOS in Integrated Circuits for Automotive Applications. [Citation Graph (, )][DBLP]


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