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Michael J. Flynn :
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Michael J. Flynn Computer Organization and Architecture. [Citation Graph (0, 0)][DBLP ] Advanced Course: Operating Systems, 1978, pp:17-98 [Conf ] Michael J. Flynn Perspective on microcomputers. [Citation Graph (0, 0)][DBLP ] Advanced Course: Microcomputer System Design, 1981, pp:1-8 [Conf ] Michael J. Flynn Customized Microcomputers. [Citation Graph (0, 0)][DBLP ] Advanced Course: Microcomputer System Design, 1981, pp:182-222 [Conf ] Manu Thapar , Bruce Delagi , Michael J. Flynn Scalable Cache Coherence for Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] ACPC, 1991, pp:1-12 [Conf ] Michael J. Flynn Time and Area Optimization in Processor Architecture. [Citation Graph (0, 0)][DBLP ] ARCS, 1997, pp:1-11 [Conf ] Hossam A. H. Fahmy , Michael J. Flynn The Case for a Redundant Format in Floating Point Arithmetic. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 2003, pp:95-0 [Conf ] Michael J. Flynn , Kevin J. Nowka , G. Bewick , Eric M. Schwarz , Nhon T. Quach The SNAP Project: Towards Sub-Nanosecond Arithmetic. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 1995, pp:75-0 [Conf ] Stuart F. Oberman , Hesham A. Al-Twaijry , Michael J. Flynn The SNAP Project: Design of Floating Point Arithmetic Unit. [Citation Graph (0, 0)][DBLP ] IEEE Symposium on Computer Arithmetic, 1997, pp:156-0 [Conf ] Michael J. Flynn Area - Time - Power and Design effort: the basic tradeoffs in Application Specific Systems. [Citation Graph (0, 0)][DBLP ] ASAP, 2005, pp:3- [Conf ] Brian P. Boesch , Michael J. Flynn Effects of Layered Protocols on Performance of a Packet Radio Network. [Citation Graph (0, 0)][DBLP ] COMPCON, 1987, pp:71-77 [Conf ] Michael J. Flynn , Curtis Spangler , Andrew Zimmerman The Stanford Packet Radio Network. [Citation Graph (0, 0)][DBLP ] COMPCON, 1986, pp:266-268 [Conf ] Daniel F. Zucker , Michael J. Flynn , Ruby B. Lee Improving Performance for MPEG Players. [Citation Graph (0, 0)][DBLP ] COMPCON, 1996, pp:327-332 [Conf ] Albert A. Liddicoat , Michael J. Flynn High-Performance Floating Point Divide. [Citation Graph (0, 0)][DBLP ] DSD, 2001, pp:354-363 [Conf ] Michael J. Flynn , Patrick Hung Computer Architecture and Technology: Some Thoughts on the Road Ahead. [Citation Graph (0, 0)][DBLP ] ERSA, 2004, pp:3-16 [Conf ] Michael J. Flynn What's ahead in computer design? [Citation Graph (0, 0)][DBLP ] EUROMICRO, 1997, pp:4-0 [Conf ] Stuart F. Oberman , Michael J. Flynn A Variable Latency Pipelined Floating-Point Adder. [Citation Graph (0, 0)][DBLP ] Euro-Par, Vol. II, 1996, pp:183-192 [Conf ] Oskar Mencer , Heiko Hübert , Martin Morf , Michael J. Flynn StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. [Citation Graph (0, 0)][DBLP ] FCCM, 2000, pp:309-312 [Conf ] Oskar Mencer , Martin Morf , Michael J. Flynn PAM-Blox: High Performance FPGA Design for Adaptive Computing. [Citation Graph (0, 0)][DBLP ] FCCM, 1998, pp:167-174 [Conf ] Hyuk-Jun Lee , Michael J. Flynn Coarse-grained carry architecture for FPGA (poster abstract). [Citation Graph (0, 0)][DBLP ] FPGA, 2000, pp:217- [Conf ] Michael J. Flynn , Albert A. Liddicoat Technology Trends and Adaptive Computing. [Citation Graph (0, 0)][DBLP ] FPL, 2001, pp:1-5 [Conf ] Oskar Mencer , Heiko Hübert , Martin Morf , Michael J. Flynn StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox. [Citation Graph (0, 0)][DBLP ] FPL, 2000, pp:595-604 [Conf ] Dwight Sunada , David Glasco , Michael J. Flynn Multiprocessor Architecture Using an Audit Trail for Fault Tolerance. [Citation Graph (0, 0)][DBLP ] FTCS, 1999, pp:40-47 [Conf ] Pradeep K. Dubey , Arvind Krishna , Michael J. Flynn Analytical Modeling of Multithreaded Pipeline Performance. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1994, pp:361-367 [Conf ] David Glasco , Bruce Delagi , Michael J. Flynn Update-Based Cache Coherence Protocols for Scalable Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] HICSS (1), 1994, pp:534-545 [Conf ] Michael J. Flynn Yesterday and Tomorrow: A View on Progress in Computer Design. [Citation Graph (0, 0)][DBLP ] ICCD, 2005, pp:239-242 [Conf ] Robert G. Wedig , Michael J. Flynn Concurrency Detection in Language-Oriented Processing Systems. [Citation Graph (0, 0)][DBLP ] ICDCS, 1982, pp:805-810 [Conf ] Daniel F. Zucker , Michael J. Flynn , Ruby B. Lee A Comparison of Hardware Prefetching Techniques for Mulimedia Benchmarks. [Citation Graph (0, 0)][DBLP ] ICMCS, 1996, pp:236-244 [Conf ] David A. Reimann , Vipin Chaudhary , Michael J. Flynn , Ishwar K. Sethi Parallel Implementation of Cone Beam Tomography. [Citation Graph (0, 0)][DBLP ] ICPP, Vol. 2, 1996, pp:170-173 [Conf ] Brian K. Bray , K. Cuderman , Michael J. Flynn , Andrew Zimmerman The Computer Architect's Workbench. [Citation Graph (0, 0)][DBLP ] IFIP Congress, 1989, pp:509-514 [Conf ] Michael J. Flynn Shared Internal Resources in Multiprocessor. [Citation Graph (0, 0)][DBLP ] IFIP Congress (1), 1971, pp:565-569 [Conf ] Michael J. Flynn Trends and Problems in Computer Organizations. [Citation Graph (0, 0)][DBLP ] IFIP Congress, 1974, pp:3-10 [Conf ] Jerome C. Huck , Michael J. Flynn Comparative Analysis of Computer Architectures. [Citation Graph (0, 0)][DBLP ] IFIP Congress, 1983, pp:699-703 [Conf ] David Glasco , Bruce Delagi , Michael J. Flynn The Impact of Cache Coherence Protocols on Systems using Fine-Grain Data Synchronization. [Citation Graph (0, 0)][DBLP ] IFIP PACT, 1994, pp:79-88 [Conf ] Manu Thapar , Bruce Delagi , Michael J. Flynn Linked List Cache Coherence for Scalable Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] IPPS, 1993, pp:34-43 [Conf ] Michael J. Flynn , Tilak Agerwala Comments on Capabilities, Limitations and Correctness of Petri Nets. [Citation Graph (0, 0)][DBLP ] ISCA, 1973, pp:81-86 [Conf ] Fabian Klass , Michael J. Flynn , A. J. van de Goor A 16x16-bit Static CMOS Wave-Pipelined Multiplier. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:143-146 [Conf ] Kevin J. Nowka , Michael J. Flynn System Design Using Wave-Pipelining: A CMOS VLSI Vector Unit. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:2301-2304 [Conf ] Brian K. Bray , Michael J. Flynn Strategies for Branch Target Buffers. [Citation Graph (0, 0)][DBLP ] MICRO, 1991, pp:42-50 [Conf ] Brian K. Bray , Michael J. Flynn Translation hint buffers to reduce access time of physically-addressed instruction caches. [Citation Graph (0, 0)][DBLP ] MICRO, 1992, pp:206-209 [Conf ] James E. Bennett , Michael J. Flynn Prediction Caches for Superscalar Processors. [Citation Graph (0, 0)][DBLP ] MICRO, 1997, pp:81-90 [Conf ] Michael J. Flynn Instruction sets and their implementations. [Citation Graph (0, 0)][DBLP ] MICRO, 1990, pp:1-6 [Conf ] Michael J. Flynn , R. I. Winner ASIC microprocessors. [Citation Graph (0, 0)][DBLP ] MICRO, 1989, pp:237-243 [Conf ] William L. Lynch , Brian K. Bray , Michael J. Flynn The effect of page allocation on caches. [Citation Graph (0, 0)][DBLP ] MICRO, 1992, pp:222-225 [Conf ] Alice Yu , Ruby B. Lee , Michael J. Flynn Performance Enhancement of H.263 Encoder Based on Zero Coefficient Prediction. [Citation Graph (0, 0)][DBLP ] ACM Multimedia, 1997, pp:21-29 [Conf ] Gregory T. Byrd , Michael J. Flynn Evaluation of Communication Mechanisms in Invalidate-Based Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP ] PCRCW, 1997, pp:159-170 [Conf ] Hyuk-Jun Lee , Albert A. Liddicoat , Michael J. Flynn Exploiting Parallelism and Data Locality of Systolic Array Applications using Multi-Ported FPGA. [Citation Graph (0, 0)][DBLP ] PDPTA, 2000, pp:- [Conf ] Fung F. Lee , Michael J. Flynn Architectural Mechanisms to Support Three-Dimensional Lattice Gas Simulations. [Citation Graph (0, 0)][DBLP ] SPAA, 1991, pp:115-122 [Conf ] Allen B. Tucker , Michael J. Flynn Dynamic Microprogramming: Processor Organization and Programming. [Citation Graph (0, 0)][DBLP ] Commun. ACM, 1971, v:14, n:4, pp:240-250 [Journal ] Michael J. Flynn Computer Engineering 30 Years After the IBM Model 91. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1998, v:31, n:4, pp:27-31 [Journal ] Michael J. Flynn , Chad L. Mitchell , Johannes M. Mulder And Now a Case for More Complex Instruction Sets. [Citation Graph (0, 0)][DBLP ] IEEE Computer, 1987, v:20, n:9, pp:71-83 [Journal ] Michael J. Flynn , Kevin W. Rudd Parallel Architectures. [Citation Graph (0, 0)][DBLP ] ACM Comput. Surv., 1996, v:28, n:1, pp:67-70 [Journal ] Michael J. Flynn , Lee W. Hoevel Measures of Ideal Execution Architectures. [Citation Graph (0, 0)][DBLP ] IBM Journal of Research and Development, 1984, v:28, n:4, pp:356-369 [Journal ] Scott P. Wakefield , Michael J. Flynn Reducing Execution Parameters Through Correspondence in Computer Architecture. [Citation Graph (0, 0)][DBLP ] IBM Journal of Research and Development, 1987, v:31, n:4, pp:420-434 [Journal ] Pradeep K. Dubey , Michael J. Flynn Optimal Pipelining. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1990, v:8, n:1, pp:10-19 [Journal ] Pradeep K. Dubey , Michael J. Flynn A Bubble Propagation Model for Pipeline Performance. [Citation Graph (0, 0)][DBLP ] J. Parallel Distrib. Comput., 1994, v:23, n:3, pp:330-337 [Journal ] Hesham A. Al-Twaijry , Stuart F. Oberman , Steve T. Fu , Michael J. Flynn The SNAP Project: Building Validated Floating Point. [Citation Graph (0, 0)][DBLP ] J. UCS, 1997, v:4, n:2, pp:99-109 [Journal ] Michael J. Flynn , Pradeep K. Dubey Guest Editors' Introduction: Hot Chips 15--Scaling the Silicon Mountain. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2004, v:24, n:2, pp:7-9 [Journal ] Michael J. Flynn , Patrick Hung Microprocessor Design Issues: Thoughts on the Road Ahead. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2005, v:25, n:3, pp:16-31 [Journal ] Michael J. Flynn , Patrick Hung , Armita Peymandoust Using Simple Tools to Evaluate Complex Architectural Trade-offs. [Citation Graph (0, 0)][DBLP ] IEEE Micro, 2000, v:20, n:4, pp:67-75 [Journal ] Michael J. Flynn , Patrick Hung CAD Tools for System-Level Modeling and Implementation. [Citation Graph (0, 0)][DBLP ] Software Focus, 2001, v:2, n:4, pp:134-139 [Journal ] Hesham A. Al-Twaijry , Michael J. Flynn Technology Scaling Effects on Multipliers. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1998, v:47, n:11, pp:1201-1215 [Journal ] Pradeep K. Dubey , George B. Adams III , Michael J. Flynn Instruction Window Size Trade-Offs and Characterization of Program Parallelism. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1994, v:43, n:4, pp:431-442 [Journal ] Pradeep K. Dubey , Michael J. Flynn Branch Strategies: Modeling and Optimization. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1991, v:40, n:10, pp:1159-1167 [Journal ] Michael J. Flynn , John L. Hennessy Parallelism and Representation Problems in Distributed Systems. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1980, v:29, n:12, pp:1060-1086 [Journal ] Michael J. Flynn , Lee W. Hoevel Execution Architecture: The DELtran Experiment. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1983, v:32, n:2, pp:156-175 [Journal ] Michael J. Flynn , John D. Johnson , Scott P. Wakefield On Instruction Sets and Their Formats. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1985, v:34, n:3, pp:242-254 [Journal ] Hans Mulder , Michael J. Flynn Processor Architecture and Data Buffering. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1992, v:41, n:10, pp:1211-1222 [Journal ] Stuart F. Oberman , Michael J. Flynn Design Issues in Division and Other Floating-Point Operations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1997, v:46, n:2, pp:154-161 [Journal ] Stuart F. Oberman , Michael J. Flynn Division Algorithms and Implementations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1997, v:46, n:8, pp:833-854 [Journal ] Nhon T. Quach , Michael J. Flynn High-Speed Addition in CMOS. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1992, v:41, n:12, pp:1612-1615 [Journal ] Eric M. Schwarz , Michael J. Flynn Hardware Starting Approximation Method and Its Application to the Square Root Operation. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1996, v:45, n:12, pp:1356-1369 [Journal ] Eric M. Schwarz , Michael J. Flynn Parallel High-Radix Nonrestoring Division. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1993, v:42, n:10, pp:1234-1246 [Journal ] Derek C. Wong , Michael J. Flynn Fast Division Using Accurate Quotient Approximations to Reduce the Number of Iterations. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1992, v:41, n:8, pp:981-995 [Journal ] Derek C. Wong , Giovanni De Micheli , Michael J. Flynn Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:25-46 [Journal ] Stuart F. Oberman , Michael J. Flynn Reducing the Mean Latency of Floating-Point Addition. [Citation Graph (0, 0)][DBLP ] Theor. Comput. Sci., 1998, v:196, n:1-2, pp:201-214 [Journal ] Daniel F. Zucker , Ruby B. Lee , Michael J. Flynn Hardware and software cache prefetching techniques for MPEG benchmarks. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:5, pp:782-796 [Journal ] Chad L. Mitchell , Michael J. Flynn The Effects of Processor Architecture on Instruction Memory Traffic. [Citation Graph (0, 0)][DBLP ] ACM Trans. Comput. Syst., 1990, v:8, n:3, pp:230-250 [Journal ] Pradeep K. Dubey , George B. Adams III , Michael J. Flynn Evaluating Performance Tradeoffs Between Fine-Grained and Coarse-Grained Alternatives. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:1, pp:17-27 [Journal ] Nhon T. Quach , Naofumi Takagi , Michael J. Flynn Systematic IEEE rounding method for high-speed floating-point multipliers. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:511-521 [Journal ] J. A. Bower , Wayne Luk , Oskar Mencer , Michael J. Flynn , Martin Morf Dynamic clock-frequencies for FPGAs. [Citation Graph (0, 0)][DBLP ] Microprocessors and Microsystems, 2006, v:30, n:6, pp:388-397 [Journal ] Michael J. Flynn Keynote Speech: Avoiding the Memory Bottleneck through Structured Arrays. [Citation Graph (0, 0)][DBLP ] IPDPS, 2007, pp:13-14 [Conf ] Stuart F. Oberman , Michael J. Flynn Minimizing the complexity of SRT tables. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:141-149 [Journal ] Oskar Mencer , Marco Platzner , Martin Morf , Michael J. Flynn Object-oriented domain specific compilers for programming FPGAs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:205-210 [Journal ] EMMY: an emulation system for user microprogramming. [Citation Graph (, )][DBLP ] Hardware starting approximation for the square root operation. [Citation Graph (, )][DBLP ] The Future Is Parallel But It May Not Be Easy. [Citation Graph (, )][DBLP ] Finding Speedup in Parallel Processors. [Citation Graph (, )][DBLP ] Spectrum of choices: superpipelined, superscalar, or multiprocessor? [Citation Graph (, )][DBLP ] Search in 0.090secs, Finished in 0.097secs