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Philippe Marquet: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jean-Luc Dekeyser, Philippe Marquet
    Supporting Irregular and Dynamic Computations in Data Parallel Languages. [Citation Graph (0, 0)][DBLP]
    The Data Parallel Programming Model, 1996, pp:197-219 [Conf]
  2. Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser
    Massively parallel processing on a chip. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2007, pp:277-286 [Conf]
  3. Sébastien Le Beux, Philippe Marquet, Ouassila Labbani, Jean-Luc Dekeyser
    FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:280-287 [Conf]
  4. Cyril Fonlupt, Jean-Luc Dekeyser, Philippe Marquet
    Dynamic Load Balancing on SIMD Data-Parallel Computers. [Citation Graph (0, 0)][DBLP]
    EUROSIM, 1994, pp:219-226 [Conf]
  5. Akram-Djellal Benalia, Jean-Luc Dekeyser, Philippe Marquet
    HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages. [Citation Graph (0, 0)][DBLP]
    HCI (2), 1993, pp:591-596 [Conf]
  6. Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser
    A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1. [Citation Graph (0, 0)][DBLP]
    HPCN, 1994, pp:338-343 [Conf]
  7. Dominique Sueur, Jean-Luc Dekeyser, Philippe Marquet
    DPFS: A Data-Parallel File System Environment. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1998, pp:940-942 [Conf]
  8. Momtchil Momtchev, Philippe Marquet
    An Asymmetric Real-Time Scheduling for Linux. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  9. Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
    Real-time systems for multiprocessor architectures. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  10. Julien Soula, Philippe Marquet, Alain Demeure, Jean-Luc Dekeyser
    Compilation Principle of a Specification Language Dedicated to Signal Processing. [Citation Graph (0, 0)][DBLP]
    PaCT, 2001, pp:358-370 [Conf]
  11. Florent Devin, Pierre Boulet, Jean-Luc Dekeyser, Philippe Marquet
    GASPARD - A Visual Parallel Programming Environment. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2002, pp:145-150 [Conf]
  12. Javed Dulloo, Philippe Marquet
    Design of a Real-Time Scheduler for Kahn Process Networks on Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2004, pp:271-277 [Conf]
  13. Éric Piel, Philippe Marquet, Julien Soula, Jean-Luc Dekeyser
    Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP. [Citation Graph (0, 0)][DBLP]
    PPAM, 2005, pp:896-903 [Conf]
  14. Arnaud Cuccuru, Jean-Luc Dekeyser, Philippe Marquet, Pierre Boulet
    Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies. [Citation Graph (0, 0)][DBLP]
    MoDELS, 2005, pp:445-459 [Conf]
  15. Jean-Luc Dekeyser, Boris Kokoszko, Jean-Luc Levaire, Philippe Marquet
    Irregular Data-Parallel Objects in C++. [Citation Graph (0, 0)][DBLP]
    VECPAR, 1996, pp:65-80 [Conf]
  16. Cyril Fonlupt, Philippe Marquet, Jean-Luc Dekeyser
    Data-Parallel Load Balancing Strategies. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1998, v:24, n:11, pp:1665-1684 [Journal]
  17. Jean-Luc Dekeyser, Dominique Lazure, Philippe Marquet
    A Geometrical Data-Parallel Language. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1994, v:29, n:4, pp:31-40 [Journal]
  18. Jean-Luc Dekeyser, Philippe Marquet, Ph. Pruex
    EVA: an explicit vector language. [Citation Graph (0, 0)][DBLP]
    SIGPLAN Notices, 1990, v:25, n:8, pp:53-71 [Journal]
  19. Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser
    Multiple Abstraction Views of FPGA to Map Parallel Applications. [Citation Graph (0, 0)][DBLP]
    ReCoSoC, 2007, pp:90-97 [Conf]

  20. A Design Flow to Map Parallel Applications onto FPGAs. [Citation Graph (, )][DBLP]


  21. Visual Data-Parallel Programming for Signal Processing Applications. [Citation Graph (, )][DBLP]


  22. Model Transformations for the Compilation of Multi-processor Systems-on-Chip. [Citation Graph (, )][DBLP]


  23. Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. [Citation Graph (, )][DBLP]


  24. Repetitive Allocation Modelling with MARTE. [Citation Graph (, )][DBLP]


  25. SOAP Based Distributed Simulation Environment for SoC Design. [Citation Graph (, )][DBLP]


  26. MDA for SoC Design, Intensive Signal Processing Experiment. [Citation Graph (, )][DBLP]


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