The SCEAS System
| |||||||

## Search the dblp DataBase
Carlo A. Furia:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Carlo A. Furia, Matteo Rossi, Dino Mandrioli, Angelo Morzenti
**Automated Compositional Proofs for Real-Time Systems.**[Citation Graph (0, 0)][DBLP] FASE, 2005, pp:326-340 [Conf] - Carlo A. Furia, Matteo Rossi
**Integrating Discrete- and Continuous-Time Metric Temporal Logics Through Sampling.**[Citation Graph (0, 0)][DBLP] FORMATS, 2006, pp:215-229 [Conf] - Andrea Matta, Carlo A. Furia, Matteo Rossi
**Semi-formal and Formal Models Applied to Flexible Manufacturing Systems.**[Citation Graph (0, 0)][DBLP] ISCIS, 2004, pp:718-728 [Conf] - Carlo A. Furia, Matteo Rossi
**A Compositional Framework for Formally Verifying Modular Systems.**[Citation Graph (0, 0)][DBLP] Electr. Notes Theor. Comput. Sci., 2005, v:116, n:, pp:185-198 [Journal] - Carlo A. Furia, Matteo Rossi, Dino Mandrioli, Angelo Morzenti
**Automated compositional proofs for real-time systems.**[Citation Graph (0, 0)][DBLP] Theor. Comput. Sci., 2007, v:376, n:3, pp:164-184 [Journal] - Carlo A. Furia, Angelo Morzenti, Matteo Pradella, Matteo Rossi
**Comments on "An Interval Logic for Real-Time System Specification'.**[Citation Graph (0, 0)][DBLP] IEEE Trans. Software Eng., 2006, v:32, n:6, pp:424-427 [Journal] - Carlo A. Furia, Matteo Rossi
**On the Expressiveness of MTL Variants over Dense Time.**[Citation Graph (0, 0)][DBLP] FORMATS, 2007, pp:163-178 [Conf] **Practical Efficient Modular Linear-Time Model-Checking.**[Citation Graph (, )][DBLP]**What's Decidable about Sequences?**[Citation Graph (, )][DBLP]**Inferring Loop Invariants Using Postconditions.**[Citation Graph (, )][DBLP]**Automated Verification of Dense-Time MTL Specifications Via Discrete-Time Approximation.**[Citation Graph (, )][DBLP]**MTL with Bounded Variability: Decidability and Complexity.**[Citation Graph (, )][DBLP]**Practical Automated Partial Verification of Multi-paradigm Real-Time Models.**[Citation Graph (, )][DBLP]**Tomorrow and All our Yesterdays: MTL Satisfiability over the Integers.**[Citation Graph (, )][DBLP]**Automated fixing of programs with contracts.**[Citation Graph (, )][DBLP]**Integrated Modeling and Verification of Real-Time Systems through Multiple Paradigms.**[Citation Graph (, )][DBLP]**Specifying Reusable Components.**[Citation Graph (, )][DBLP]**Practical Automated Partial Verification of Multi-Paradigm Real-Time Models**[Citation Graph (, )][DBLP]**Modeling Time in Computing: A Taxonomy and a Comparative Survey**[Citation Graph (, )][DBLP]**On Relaxing Metric Information in Linear Temporal Logic**[Citation Graph (, )][DBLP]**Integrated Modeling and Verification of Real-Time Systems through Multiple Paradigms**[Citation Graph (, )][DBLP]**Inferring Loop Invariants using Postconditions**[Citation Graph (, )][DBLP]**A Theory of Sampling for Continuous-time Metric Temporal Logic**[Citation Graph (, )][DBLP]**What's Decidable About Sequences?**[Citation Graph (, )][DBLP]**Refinement and Verification of Real-Time Systems**[Citation Graph (, )][DBLP]**Specifying Reusable Components**[Citation Graph (, )][DBLP]**Comments on temporal logics for real-time system specification.**[Citation Graph (, )][DBLP]**Modeling time in computing: A taxonomy and a comparative survey.**[Citation Graph (, )][DBLP]
Search in 0.004secs, Finished in 0.005secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |