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Publications of Author

1. Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman
   A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. [Citation Graph (0, 0)][DBLP]
   FCCM, 1999, pp:304-305 [Conf]
   
2. Hanho Lee, Gerald E. Sobelman
   Digit-Serial DSP Library for Optimized FPGA Configuration. [Citation Graph (0, 0)][DBLP]
   FCCM, 1998, pp:322-323 [Conf]
   
3. Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman
   FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). [Citation Graph (0, 0)][DBLP]
   FPGA, 1998, pp:257- [Conf]
   
4. Hanho Lee, Gerald E. Sobelman
   A New Low-Voltage Full Adder Circuit. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1997, pp:88-0 [Conf]
   
5. Hanho Lee
   High-speed VLSI architecture for parallel Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2003, pp:320-323 [Conf]
   
6. Hanho Lee
   An ultra high-speed Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
   ISCAS (2), 2005, pp:1036-1039 [Conf]
   
7. Hanho Lee
   An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2003, pp:209-210 [Conf]
   
8. In Ja Jeon, Phill-Kyu Rhee, Hanho Lee
   An Evolvable Hardware System Under Uneven Environment. [Citation Graph (0, 0)][DBLP]
   KES (2), 2005, pp:319-326 [Conf]
   
9. Hanho Lee
   Reconfigurable Power-Aware Scalable Booth Multiplier. [Citation Graph (0, 0)][DBLP]
   KES (1), 2005, pp:176-183 [Conf]
   
10. Hanho Lee, Chang-Seok Choi
    Implementation of a FIR Filter on a Partial Reconfigurable Platform. [Citation Graph (0, 0)][DBLP]
    KES (3), 2006, pp:108-115 [Conf]
    
11. Hanho Lee, Gerald E. Sobelman
    VLSI Design Of Digit-Serial FPGA Architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2004, v:13, n:1, pp:17-52 [Journal]
    
12. Seungbeom Lee, Hanho Lee, Jongyoon Shin, Je-Soo Ko
    A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:901-904 [Conf]
    
13. Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
    A reconfigurable FIR filter design using dynamic partial reconfiguration. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
14. Jeesung Lee, Hanho Lee, Sang-in Cho, Sang-Sung Choi
    A high-speed, low-complexity radix-2⁴ FFT processor for MB-OFDM UWB systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
15. Yong-min Lee, Chang-Seok Choi, Seung-Gon Hwang, Hyun Dong Kim, Chul Hong Min, Jae-Hyun Park, Hanho Lee, Tae-Seon Kim, Chong Ho Lee
    Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. [Citation Graph (0, 0)][DBLP]
    ARC, 2007, pp:283-292 [Conf]
    
16. Yeong-Jae Oh, Hanho Lee, Chong Ho Lee
    Dynamic Partial Reconfigurable FIR Filter Design. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:30-35 [Conf]
    
17. Hanho Lee
    High-speed VLSI architecture for parallel Reed-Solomon decoder. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:2, pp:288-294 [Journal]
    
18. 
    Adaptive quantization in min-sum based irregular LDPC decoder. [Citation Graph (, )][DBLP]
    
    
19. 
    Two bit-level pipelined viterbi decoder for high-performance UWB applications. [Citation Graph (, )][DBLP]
    
    
20. 
    A high-speed four-parallel radix-2⁴ FFT/IFFT processor for UWB applications. [Citation Graph (, )][DBLP]
    
    
21. 
    A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders. [Citation Graph (, )][DBLP]
    
    
22. 
    A Partial Self-Reconfigurable Adaptive FIR Filter System. [Citation Graph (, )][DBLP]
    
    
23. 
    Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications. [Citation Graph (, )][DBLP]