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Publications of Author

1. Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki
   Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:315-316 [Conf]
   
2. Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima
   Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
   FCCM, 2004, pp:328-329 [Conf]
   
3. Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano
   Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. [Citation Graph (0, 0)][DBLP]
   FPGA, 2005, pp:265- [Conf]
   
4. Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa
   An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? [Citation Graph (0, 0)][DBLP]
   FPL, 2005, pp:347-352 [Conf]
   
5. Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima
   An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
   FPT, 2005, pp:163-170 [Conf]
   
6. Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano
   A cost-effective context memory structure for dynamically reconfigurable processors. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
7. Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, T. Nakamura, T. Nishimura, Hideharu Amano
   Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2006, pp:- [Conf]
   
8. Takashi Egawa, Koji Hino, Yohei Hasegawa
   Fast and Secure Packet Processing Environment for Per-Packet QoS Customization. [Citation Graph (0, 0)][DBLP]
   IWAN, 2001, pp:34-48 [Conf]
   
9. Hideharu Amano, Yohei Hasegawa, Shohei Abe, K. Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, T. Nakamura, T. Nishimura
   A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. [Citation Graph (0, 0)][DBLP]
   FPL, 2006, pp:1-6 [Conf]
   
10. Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano
    Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:115-121 [Conf]
    
11. 
    Cache Controller Design on Ultra Low Leakage Embedded Processors. [Citation Graph (, )][DBLP]
    
    
12. 
    Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. [Citation Graph (, )][DBLP]
    
    
13. 
    Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. [Citation Graph (, )][DBLP]
    
    
14. 
    Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP]
    
    
15. 
    Power reduction techniques for Dynamically Reconfigurable Processor Arrays. [Citation Graph (, )][DBLP]
    
    
16. 
    Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. [Citation Graph (, )][DBLP]
    
    
17. 
    MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. [Citation Graph (, )][DBLP]
    
    
18. 
    A fine-grain dynamic sleep control scheme in MIPS R3000. [Citation Graph (, )][DBLP]
    
    
19. 
    Deployable multipath communication scheme with sufficient performance data distribution method. [Citation Graph (, )][DBLP]