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Roger Woods: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Timothy Courtney, Richard H. Turner, Roger Woods
    An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:341-343 [Conf]
  2. Tim Courtney, Richard H. Turner, Roger Woods
    Mapping Multi-Mode Circuits to LUT-Based FPGA Using Embedded MUXes. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:318-0 [Conf]
  3. Jean-Paul Heron, Roger Woods
    Accelerating Run-Time Reconfiguration on FCCMs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:260-261 [Conf]
  4. Richard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron
    A Virtual Hardware Handler for RTR Systems. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:262-263 [Conf]
  5. Sakir Sezer, Roger Woods, Jean-Paul Heron, Alan Marshall
    Fast Partial Reconfiguration for FCCMs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:318-319 [Conf]
  6. Roger Woods, Stefan H.-M. Ludwig, Jean-Paul Heron, David W. Trainor, Stephan W. Gehring
    FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again). [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:155-164 [Conf]
  7. Tim Courtney, Richard H. Turner, Roger Woods
    Multiplexer Based Reconfiguration for Virtex Multipliers. [Citation Graph (0, 0)][DBLP]
    FPL, 2000, pp:749-758 [Conf]
  8. Jean-Paul Heron, Roger Woods
    Architectural Strategies for Implementing an Image Processing Algorithm on XC6000 FPGA. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:317-326 [Conf]
  9. Lok-Kee Ting, Roger Woods, Colin Cowan
    Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver. [Citation Graph (0, 0)][DBLP]
    FPL, 2001, pp:367-376 [Conf]
  10. David W. Trainor, Roger Woods
    Architectural Synthesis and Efficient Circuit Implementation for Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    FPL, 1996, pp:116-125 [Conf]
  11. Richard H. Turner, Roger Woods
    Design Flow for Efficient FPGA Reconfiguration. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:972-975 [Conf]
  12. Richard H. Turner, Roger Woods, Tim Courtney
    Multiplier-less Realization of a Poly-phase Filter Using LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:192-201 [Conf]
  13. S. Fischaber, R. Hasson, John McAllister, Roger Woods
    FPGA Core Network Implementation and Optimization: A Case Study. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:319-320 [Conf]
  14. Erdem Motuk, Roger Woods, Stefan Bilbao
    FPGA-Based Hardware for Physical Modelling Sound Synthesis by Finite Difference Schemes. [Citation Graph (0, 0)][DBLP]
    FPT, 2005, pp:103-110 [Conf]
  15. Shane O'Neill, Alan Marshall, Roger Woods
    Providing Input-Output Throughput Guarantees in a Buffered Crossbar Switch. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:725-730 [Conf]
  16. Gareth Keane, Jonathan Spanier, Roger Woods
    The impact of data characteristics and hardware topology on hardware selection for low power DSP. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:94-96 [Conf]
  17. Shane O'Neill, Alan Marshall, Roger Woods
    A Novel Packet Marking Function for Real-Time Interactive MPEG-4 Video Applications in a Differentiated Services Network. [Citation Graph (0, 0)][DBLP]
    NETWORKING, 2005, pp:1031-1042 [Conf]
  18. John McAllister, Roger Woods, D. Reilly, S. Fischaber, R. Hasson
    Rapid Implementation and Optimisation of DSP Systems on SoPC Heterogeneous Platforms. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2005, pp:414-423 [Conf]
  19. John McAllister, Roger Woods, Richard Walke
    Embedded Context Aware Hardware Component Generation for Dataflow System Exploration. [Citation Graph (0, 0)][DBLP]
    SAMOS, 2004, pp:254-263 [Conf]
  20. Roger Woods, David W. Trainor, Jean-Paul Heron
    Applying an XC6200 to Real-Time Image Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:30-38 [Journal]
  21. Lok-Kee Ting, Roger Woods, C. F. N. Cowan
    Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:86-95 [Journal]
  22. Brendan McAllister, Alan Marshall, Roger Woods
    Programmable Network Functionality for Improved QoS of Interactive Video Traffic. [Citation Graph (0, 0)][DBLP]
    Net-Con, 2005, pp:283-296 [Conf]
  23. John McAllister, Roger Woods, S. Fischaber, E. Malins
    Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2007, v:53, n:8, pp:511-523 [Journal]
  24. G. Lightbody, Roger Woods, Richard Walke
    Design of a parameterizable silicon intellectual property core for QR-based RLS filtering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:659-678 [Journal]
  25. John McAllister, Roger Woods, Richard Walke, D. Reilly
    Multidimensional DSP Core Synthesis for FPGA. [Citation Graph (0, 0)][DBLP]
    VLSI Signal Processing, 2006, v:43, n:2-3, pp:207-221 [Journal]

  26. QR Recursive Least Squares IP Core Example. [Citation Graph (, )][DBLP]

  27. Muir Hardware Synthesis for Multimedia Applications. [Citation Graph (, )][DBLP]

  28. Power efficient DSP datapath configuration methodology for FPGA. [Citation Graph (, )][DBLP]

  29. Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. [Citation Graph (, )][DBLP]

  30. An Attack-Resilent Sampling Mechanism for Integrated IP Flow Monitors. [Citation Graph (, )][DBLP]

  31. Memory-Centric Hardware Synthesis from Dataflow Models. [Citation Graph (, )][DBLP]

  32. A real-time flow monitor architecture encompassing on-demand monitoring functions. [Citation Graph (, )][DBLP]

  33. SOC Memory Hierarchy Derivation from Dataflow Graphs. [Citation Graph (, )][DBLP]

  34. Power efficient dynamic-range utilisation for DSP on FPGA. [Citation Graph (, )][DBLP]

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