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Abdsamad Benkrid:
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- Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
Design and Implementation of a Generic 2-D Orthogonal Discrete Wavelet Transform on FPGA. [Citation Graph (0, 0)][DBLP] FCCM, 2003, pp:162-172 [Conf]
- Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP] FCCM, 2003, pp:273-275 [Conf]
- Abdsamad Benkrid, Danny Crookes, Khaled Benkrid
Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA. [Citation Graph (0, 0)][DBLP] FPGA, 2003, pp:238- [Conf]
- Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP] FPL, 2003, pp:553-564 [Conf]
- Khaled Benkrid, Danny Crookes, Abdsamad Benkrid, S. Belkacemi
A Prolog-Based Hardware Development Environment. [Citation Graph (0, 0)][DBLP] FPL, 2002, pp:370-380 [Conf]
- Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid
An FPGA-Based Image Connected Component Labeller. [Citation Graph (0, 0)][DBLP] FPL, 2003, pp:1012-1015 [Conf]
- Danny Crookes, Khalid Alotaibi, Ahmed Bouridane, Paul Donachy, Abdsamad Benkrid
An Environment for Generating FPGA Architectures for Image Algebra-based Algorithms. [Citation Graph (0, 0)][DBLP] ICIP (3), 1998, pp:990-994 [Conf]
- Khaled Benkrid, Danny Crookes, Abdsamad Benkrid
Design and implementation of a novel algorithm for general purpose median filtering on FPGAs. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2002, pp:425-428 [Conf]
- Abdsamad Benkrid, Khaled Benkrid, Danny Crookes
Design and Implementation of Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs. [Citation Graph (0, 0)][DBLP] ISVLSI, 2004, pp:222-225 [Conf]
- Khaled Benkrid, Abdsamad Benkrid, S. Belkacemi
Efficient FPGA hardware development: A multi-language approach. [Citation Graph (0, 0)][DBLP] Journal of Systems Architecture, 2007, v:53, n:4, pp:184-209 [Journal]
- Khaled Benkrid, Danny Crookes, Abdsamad Benkrid
Towards a general framework for FPGA based image processing using hardware skeletons. [Citation Graph (0, 0)][DBLP] Parallel Computing, 2002, v:28, n:7-8, pp:1141-1154 [Journal]
- Abdsamad Benkrid, Khaled Benkrid
Handling finite length signals borders in two-channel multirate filter banks for perfect reconstruction. [Citation Graph (0, 0)][DBLP] Signal Processing, 2006, v:86, n:2, pp:375-387 [Journal]
- Khaled Benkrid, S. Belkacemi, Abdsamad Benkrid
HIDE: A hardware intelligent description environment. [Citation Graph (0, 0)][DBLP] Microprocessors and Microsystems, 2006, v:30, n:6, pp:283-300 [Journal]
Design and Implementation of a Highly Parameterised FPGA-Based Skeleton for Pairwise Biological Sequence Alignment. [Citation Graph (, )][DBLP]
High Performance Biosequence Database Scanning using FPGAs. [Citation Graph (, )][DBLP]
HIDE+: A Logic Based Hardware Development Environment. [Citation Graph (, )][DBLP]
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