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Publications of Author

1. Andrea Cappelli, Andrea Lodi, Claudio Mucci, Mario Toma, Fabio Campi
   A Dataflow Control Unit for C-to-Configurable Pipelines Compilation Flow. [Citation Graph (0, 0)][DBLP]
   FCCM, 2004, pp:332-333 [Conf]
   
2. Andrea Lodi, Luca Ciccarelli, Claudio Mucci, Roberto Giansante, Andrea Cappelli, Mario Toma
   An Embedded Reconfigurable Datapath for SoC. [Citation Graph (0, 0)][DBLP]
   FCCM, 2005, pp:303-304 [Conf]
   
3. Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Mario Toma, Fabio Campi
   Routing architecture for multi-context FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 2004, pp:246- [Conf]
   
4. Andrea Lodi, Mario Toma, Fabio Campi
   A pipelined configurable gate array for embedded processors. [Citation Graph (0, 0)][DBLP]
   FPGA, 2003, pp:21-30 [Conf]
   
5. Andrea Lodi, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma
   Compact Buffered Routing Architecture. [Citation Graph (0, 0)][DBLP]
   FPL, 2004, pp:179-188 [Conf]
   
6. Fabio Campi, Andrea Cappelli, Roberto Guerrieri, Andrea Lodi, Mario Toma, Alberto La Rosa, Luciano Lavagno, Claudio Passerone, Roberto Canegallo
   A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:171- [Conf]
   
7. Andrea Lodi, Carlo Chiesa, Fabio Campi, Mario Toma
   A flexible LUT-based carry chain for FPGAs. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2003, pp:133-136 [Conf]
   
8. Andrea Lodi, Luca Ciccarelli, Andrea Cappelli, Fabio Campi, Mario Toma
   Decoder-Based Multi-Context Interconnect Architecture. [Citation Graph (0, 0)][DBLP]
   ISVLSI, 2003, pp:231-233 [Conf]
   
9. Claudio Mucci, Luca Vanzolini, Fabio Campi, Mario Toma
   Interactive presentation: Implementation of AES/Rijndael on a dynamically reconfigurable architecture. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:355-360 [Conf]
   
10. Claudio Mucci, Massimo Bocchi, Mario Toma, Fabio Campi
    A case-study on multimedia applications for the XiRisc reconfigurable processor. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]