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Raj Krishnamurthy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
    ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers. [Citation Graph (0, 0)][DBLP]
    FCCM, 2004, pp:115-124 [Conf]
  2. Richard West, Raj Krishnamurthy, W. K. Norton, Karsten Schwan, Sudhakar Yalamanchili, Marcel-Catalin Rosu, V. Sarat
    QUIC: A Quality of Service Network Interface Layer for Communication in NOWs. [Citation Graph (0, 0)][DBLP]
    Heterogeneous Computing Workshop, 1999, pp:199-208 [Conf]
  3. Cyriel Minkenberg, François Abel, Peter Müller, Raj Krishnamurthy, Mitchell Gusat, B. Roe Hemenway
    Control Path Implementation for a Low-Latency Optical HPC Switch. [Citation Graph (0, 0)][DBLP]
    Hot Interconnects, 2005, pp:29-35 [Conf]
  4. Raj Krishnamurthy, Karsten Schwan, Richard West, Marcel-Catalin Rosu
    A Network Co-Processor-Based Approach to Scalable Media Streaming in Servers. [Citation Graph (0, 0)][DBLP]
    ICPP, 2000, pp:125-134 [Conf]
  5. Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West
    Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2003, pp:30- [Conf]
  6. Cyriel Minkenberg, François Abel, Peter Müller, Raj Krishnamurthy, Mitchell Gusat, Peter Dill, Ilias Iliadis, Ronald P. Luijten, B. Roe Hemenway, Richard Grzybowski, Enrico Schiattarella
    Designing a Crossbar Scheduler for HPC Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:3, pp:58-71 [Journal]
  7. Raj Krishnamurthy, Karsten Schwan, Richard West, Marcel-Catalin Rosu
    On Network CoProcessors for Scalable, Predictable Media Services. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2003, v:14, n:7, pp:655-670 [Journal]

  8. Architecture and Hardware for Scheduling Gigabit Packet Streams. [Citation Graph (, )][DBLP]


  9. An Input Queueing Implementation for Low-Latency Speculative Optical Switches. [Citation Graph (, )][DBLP]


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